ATxmega16A4U Atmel Corporation, ATxmega16A4U Datasheet - Page 444

• Manufacturer Part Number: ATxmega16A4U
• Manufacturer: Atmel Corporation

Specifications of ATxmega16A4U

• Flash (kbytes): 16 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 7
• Twi (i2c): 2
• Uart: 5
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 3.3
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 16
• Pwm Channels: 16
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

33.12.1
33.12.2
33.12.3
8331A–AVR–07/11
CMD[6:0]
Flash Page Buffer
Flash
0x00
0x40
0x43
0x23
0x26
Enabling External Programming Interface
NVM Programming
NVM Commands
Commands / Operation
No Operation
Chip Erase
Read NVM
Load Flash Page Buffer
Erase Flash Page Buffer
(1)
NVM programming from the PDI requires enabling, and using the following steps:
When the NVMEN bit in the PDI STATUS register is set the NVM interface is enabled and active
from the PDI.
When the PDI NVM interface is enabled, all memories in the device are memory-mapped in the
PDI address space. The PDI controller does not need to access the NVM controller's address or
data registers, but the NVM controller must be loaded with the correct command (i.e. to read
from any NVM, the controller must be loaded with the NVM Read command before loading data
from the PDIBUS address space). For the reminder of this section all references to reading and
writing data or program memory addresses from PDI, refer to the memory map as shown in
ure 33-3 on page
The PDI uses byte addressing, hence all memory addresses must be byte addresses. When fill-
ing the Flash or EEPROM page buffers, only the least significant bits of the address are used to
determine locations within the page buffer. Still, the complete memory mapped address for the
Flash or EEPROM page is required to ensure correct address mapping.
During programming (page erase and page write) when the NVM is busy, the NVM is blocked for
reading.
The NVM commands that can be used for accessing the NVM memories from external program-
ming are listed in
self-programming.
For external programming, the Trigger for Action Triggered Commands is to set the CMDEX bit
in the NVM CTRLA register (CMDEX). The Read Triggered Commands are triggered by a direct
or indirect Load instruction (LDS or LD) from the PDI (PDI Read). The Write Triggered Com-
mands is triggered by a direct or indirect Store instruction (STS or ST) from the PDI (PDI Write).
”Chip Erase” on page 445
rithm for each NVM operation. The commands are protected by the Lock Bits, and if Read and
Write Lock is set, only the Chip Erase and Flash CRC commands are available.
Table 33-5.
1. Load the RESET register in the PDI with 0x59.
2. Load the NVM key in the PDI.
3. Poll NVMEN in the PDI Status Register (PDI STATUS) until NVMEN is set.
NVM commands available for external programming
443.
Table 33-5 on page
through
”Write Fuse/ Lock Bit” on page 448
444. This is a super-set of the commands available for
Atmel AVR XMEGA AU
Trigger
-
CMDEX
PDI Read
PDI Write
CMDEX
explains in detail the algo-
Change
Protected
Y
N
N
Y
-
NVM Busy
Y
N
N
Y
-
Fig-
444