ATxmega16A4U Atmel Corporation, ATxmega16A4U Datasheet - Page 438

• Manufacturer Part Number: ATxmega16A4U
• Manufacturer: Atmel Corporation

Specifications of ATxmega16A4U

• Flash (kbytes): 16 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 7
• Twi (i2c): 2
• Uart: 5
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 3.3
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 16
• Pwm Channels: 16
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

33.11.2.14
33.11.3
Table 33-3.
33.11.3.1
8331A–AVR–07/11
CMD[6:0]
0x00
Fuses and Lock Bits
0x07
0x08
NVM Fuse and Lock Bit Commands
Group Configuration
NO_OPERATION
READ_FUSES
WRITE_LOCK_BITS
Read User Signature Row / Calibration Row
Write Lock Bits Write
Fuse and Lock Bit Commands
The Read User Signature Row and Read Calibration Row commands are used to read one byte
from the User Signature Row or Calibration Row.
The destination register will be loaded during the execution of the LPM instruction.
To ensure that LPM for reading flash will be executed correctly it is adviced to disable interrupt
while using either of these commands.
The NVM Flash commands that can be used for accessing the Fuses and Lock Bits are listed in
Table
For self-programming of the Fuses and Lock Bits, the Trigger for Action Triggered Commands is
to set the CMDEX bit in the NVM CTRLA register (CMDEX). The Read Triggered Commands
are triggered by executing the (E)LPM instruction (LPM). The Write Triggered Commands is trig-
gered by a executing the SPM instruction (SPM).
The Change Protected column indicates if the trigger is protected by the Configuration Change
Protection (CCP) during self-programming or not. The last two columns show the address
pointer used for addressing, and the source/destination data register.
Section 33.11.3.1 on page 438
algorithm for each NVM operation.
The Write Lock Bits command is used to program the Boot Lock Bits to a more secure settings
from software.
1.
2.
3.
during self-programming.
The BUSY flag in the NVM STATUS register will be set until the command is finished. The CPU
is halted during the complete execution of the command.
This command can be executed from both the Boot Loader Section and the Application Section.
The EEPROM and Flash Page Buffer is automatically erased when the Lock Bits are written.
1. Load the Z-pointer with the byte address to read.
2. Load the NVM CMD register with the Read User Signature Row / Calibration Row
3. Execute the LPM instruction.
command
Load the NVM DATA0 register with the new Lock bit value.
Load the NVM CMD register with the Write Lock Bit command.
Set the CMDEX bit in the NVM CTRLA register. This requires the timed CCP sequence
33-3.
Description
No Operation
Read Fuses
Write Lock Bits
through
Trigger
CMDEX
CMDEX
-
Section 33.11.3.2 on page 439
CPU
Halted
Y
N
-
Atmel AVR XMEGA AU
Change
Protected
N
Y
-
NVM
Busy
Y
Y
-
explain in details the
Address
pointer
ADDR
ADDR
-
Data
register
DATA
-
-
438