ATxmega16A4U Atmel Corporation, ATxmega16A4U Datasheet - Page 53

• Manufacturer Part Number: ATxmega16A4U
• Manufacturer: Atmel Corporation

Specifications of ATxmega16A4U

• Flash (kbytes): 16 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 7
• Twi (i2c): 2
• Uart: 5
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 3.3
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 16
• Pwm Channels: 16
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

5. DMAC - Direct Memory Access Controller
5.1
5.2
8331A–AVR–07/11
Features
Overview
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The four-channel direct memory access (DMA) controller can transfer data between memories
and peripherals, and thus offload these tasks from the CPU. It enables high data transfer rates
with minimum CPU intervention, and frees up CPU time. The four DMA channels enable up to
four independent and parallel transfers.
The DMA controller can move data between SRAM and peripherals, between SRAM locations
and directly between peripheral registers. With access to all peripherals, the DMA controller can
handle automatic transfer of data to/from communication modules. The DMA controller can also
read from memory mapped EEPROM.
Data transfers are done in continuous bursts of 1, 2, 4, or 8 bytes. They build block transfers of
configurable size from 1 byte to 64KB. A repeat counter can be used to repeat each block trans-
fer for single transactions up to 16MB. Source and destination addressing can be static,
incremental or decremental. Automatic reload of source and/or destination addresses can be
done after each burst or block transfer, or when a transaction is complete. Application software,
peripherals, and events can trigger DMA transfers.
The four DMA channels have individual configuration and control settings. This include source,
destination, transfer triggers, and transaction sizes. They have individual interrupt settings. Inter-
rupt requests can be generated when a transaction is complete or when the DMA controller
detects an error on a DMA channel.
Allows high speed data transfers with minimal CPU intervention
Four DMA channels with separate
Programmable channel priority
From 1 byte to 16MB of data in a single transaction
Multiple addressing modes
Optional reload of source and destination addresses at the end of each
Optional interrupt on end of transaction
Optional connection to CRC generator for CRC on DMA data
– from data memory to data memory
– from data memory to peripheral
– from peripheral to data memory
– from peripheral to peripheral
– transfer triggers
– interrupt vectors
– addressing modes
– Up to 64KB block transfers with repeat
– 1, 2, 4, or 8 byte burst transfers
– Static
– Incremental
– Decremental
– Burst
– Block
– Transaction
Atmel AVR XMEGA AU
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