ATxmega192A3U Atmel Corporation, ATxmega192A3U Datasheet - Page 267

• Manufacturer Part Number: ATxmega192A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega192A3U

• Flash (kbytes): 192 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 21-12. TWI master operation.
21.5.1
21.5.1.1
8331A–AVR–07/11
SW
APPLICATION
M1
Transmitting Address Packets
SW
Mn
Case M1: Arbitration lost or bus error during address packet
BUSY
Wait for
IDLE
Driver software
The master provides data
on the bus
Slave provides data on
the bus
Bus state
Diagram connections
M2
P
When an interrupt flag is set, the SCL line is forced low. This will give the master time to respond
or handle any data, and will in most cases require software interaction.
TWI master operation. The diamond shaped symbols (SW) indicate where software interaction
is required. Clearing the interrupt flags releases the SCL line.
The number of interrupts generated is kept to a minimum by automatic handling of most condi-
tions. Quick command and smart mode can be enabled to auto-trigger operations and reduce
software complexity.
After issuing a START condition, the master starts performing a bus transaction when the mas-
ter address register is written with the 7-bit slave address and direction bit. If the bus is busy, the
TWI master will wait until the bus becomes idle before issuing the START condition.
Depending on arbitration and the R/W direction bit, one of four distinct cases (M1 to M4) arises
following the address packet. The different cases must be handled in software.
If arbitration is lost during the sending of the address packet, the master write interrupt flag and
arbitration lost flag are both set. Serial data output to the SDA line is disabled, and the SCL line
is released. The master is no longer allowed to perform any operation on the bus until the bus
state has changed back to idle.
A bus error will behave in the same way as an arbitration lost condition, but the error flag is set in
addition to the write interrupt and arbitration lost flags.
IDLE
M3
S
ADDRESS
R/W
R/W
W
R
BUSY
A
A
A
M4
MASTER WRITE INTERRUPT + HOLD
MASTER READ INTERRUPT + HOLD
SW
SW
SW
SW
SW
Atmel AVR XMEGA AU
A/A
A/A
A/A
A
BUSY
BUSY
Sr
Sr
P
P
IDLE
IDLE
DATA
M1
M2
M3
M4
M2
M3
Figure 21-12
DATA
A/A
BUSY
shows the
M4
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