ATxmega192A3U Atmel Corporation, ATxmega192A3U Datasheet - Page 54

• Manufacturer Part Number: ATxmega192A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega192A3U

• Flash (kbytes): 192 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

5.3
5.3.1
5.3.2
5.4
8331A–AVR–07/11
DMA Transaction
Transfer Triggers
Block Transfer and Repeat
Burst Transfer
To allow for continuous transfers, two channels can be interlinked so that the second takes over
the transfer when the first is finished, and vice versa.
A complete DMA read and write operation between memories and/or peripherals is called a
DMA transaction. A transaction is done in data blocks, and the size of the transaction (number of
bytes to transfer) is selectable from software and controlled by the block size and repeat counter
settings. Each block transfer is divided into smaller bursts.
The size of the block transfer is set by the block transfer count register, and can be anything
from 1 byte to 64KB.
A repeat counter can be enabled to set a number of repeated block transfers before a transac-
tion is complete. The repeat is from 1 to 255, and an unlimited repeat count can be achieved by
setting the repeat count to zero.
Since the AVR CPU and DMA controller use the same data buses, a block transfer is divided
into smaller burst transfers. The burst transfer is selectable to 1, 2, 4, or 8 bytes. This means that
if the DMA acquires the data bus and a transfer request is pending, it will occupy the bus until all
bytes in the burst are transferred.
A bus arbiter controls when the DMA controller and the AVR CPU can use the bus. The CPU
always has priority, and so as long as the CPU requests access to the bus, any pending burst
transfer must wait. The CPU requests bus access when it executes an instruction that writes or
reads data to SRAM, I/O memory, EEPROM or the external bus interface. For more details on
memory access bus arbitration, refer to
Figure 5-1.
DMA transfers can be started only when a DMA transfer request is detected. A transfer request
can be triggered from software, from an external trigger source (peripheral), or from an event.
There are dedicated source trigger selections for each DMA channel. The available trigger
sources may vary from device to device, depending on the modules or peripherals that exist in
the device. Using a transfer trigger for a module or peripherals that does not exist will have no
Four-byte burst mode
DMA transaction.
Burst transfer
Block size: 12 bytes
”Data Memory” on page
DMA transaction
Repeat count: 2
Atmel AVR XMEGA AU
Block transfer
22.
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