ATxmega192A3U Atmel Corporation, ATxmega192A3U Datasheet - Page 350

• Manufacturer Part Number: ATxmega192A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega192A3U

• Flash (kbytes): 192 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

27.11.3
8331A–AVR–07/11
CTRLB (SDRAM) – Control Register B
• Bit 2:0 – SRWS[2:0]: SRAM Wait State
These bits select the number of wait states for SRAM and SRAM LPC access as a number of
Clk
Table 27-23. Wait State selection
This configuration options in this register depend on the Chip Select Mode configuration. The
register description below is valid when the Chip Select Mode is configured for SDRAM
• Bit 7 – SDINITDONE: SDRAM Initialization Complete
This flag is set at the end of the SDRAM initialization sequence. The flag will remain set as long
as the EBI is enabled and the Chip Select is configured for SDRAM.
• Bit 6:3 – Reserved
These bits are reserved and will always be read as zero.
• Bit 2 – SDSREN: SDRAM Self-refresh Enable
When this bit is written to one the EBI controller will send a Self-refresh command to the
SDRAM. For leaving the self refresh mode, the bit must be written to zero.
• Bit 1:0 SDMODE[1:0]: SDRAM Mode
These bits select mode when accessing the SDRAM according to
Table 27-24. SDRAM Mode
Bit
+0x01
Read/Write
Initial Value
SDMODE[1:0]
PER2
SRWS[2:0]
00
01
10
11
cycles, according to
000
001
010
011
100
101
110
111
SDINITDONE
R/W
7
0
NORMAL
LOAD
-
-
Group Configuration
Group Configuration
0CLK
1CLK
2CLK
3CLK
4CLK
5CLK
6CLK
7CLK
Table 27-23 on page
R
6
0
–
R
5
–
0
Normal Mode. Access to the SDRAM is decoded normally.
Load Mode. The EBI issues a “Load Mode Register”
command when the SDRAM is accessed.
Reserved
Reserved
Description
R
4
0
–
Description
0 Clk
1 Clk
2 Clk
3 Clk
4 Clk
5 Clk
6 Clk
7 Clk
350.
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
Atmel AVR XMEGA AU
R
3
0
–
cycles wait state
cycles wait state
cycles wait state
cycles wait state
cycles wait state
cycles wait state
cycles wait state
cycles wait state
SDREN
R/W
2
0
Table 27-24 on page
R/W
SDMODE[1:0]
1
0
R/W
0
0
.
CTRLB
350.
350