ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 135

• Manufacturer Part Number: ATxmega256A3BU
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3BU

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

12.5
12.6
12.6.1
8331A–AVR–07/11
Interrupt level
Interrupt priority
Static priority
The interrupt level is independently selected for each interrupt source. For any interrupt request,
the PMIC also receives the interrupt level for the interrupt. The interrupt levels and their corre-
sponding bit values for the interrupt level configuration of all interrupts is shown in
Table 12-1.
The interrupt level of an interrupt request is compared against the current level and status of the
interrupt controller. An interrupt request of a higher level will interrupt any ongoing interrupt han-
dler from a lower level interrupt. When returning from the higher level interrupt handler, the
execution of the lower level interrupt handler will continue.
Within each interrupt level, all interrupts have a priority. When several interrupt requests are
pending, the order in which interrupts are acknowledged is decided both by the level and the pri-
ority of the interrupt request. Interrupts can be organized in a static or dynamic (round-robin)
priority scheme. High- and medium-level interrupts and the NMI will always have static priority.
For low-level interrupts, static or dynamic priority scheduling can be selected.
Interrupt vectors (IVEC) are located at fixed addresses. For static priority, the interrupt vector
address decides the priority within one interrupt level, where the lowest interrupt vector address
has the highest priority. Refer to the device datasheet for the interrupt vector table with the base
address for all modules and peripherals with interrupt capability. Refer to the interrupt vector
summary of each module and peripheral in this manual for a list of interrupts and their corre-
sponding offset address within the different modules and peripherals.
Interrupt Level
Configuration
00
01
10
11
Interrupt levels.
Group Configuration
MED
OFF
LO
HI
Atmel AVR XMEGA AU
Description
Interrupt disabled.
Low-level interrupt
Medium-level interrupt
High-level interrupt
Table
12-1.
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