ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 247

• Manufacturer Part Number: ATxmega256A3BU
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3BU

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

20.13.4
20.13.5
20.13.6
8331A–AVR–07/11
ADDR – Address Register
FIFOWP – FIFO Write Pointer Register
FIFORP – FIFO Read Pointer Register
• Bit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
• Bit 6:0 – ADDR[6:0]: Device Address
These bits contain the USB address the device will respond to.
• Bit 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 4:0 – FIFOWP[4:0]: FIFO Write Pointer
These bits contain transaction complete FIFO write pointer. This register must only be read by
the CPU / DMA Controller. Writing this register will flush the FIFO write and read pointers.
• Bit 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 4:0 – FIFORP[4:0]: FIFO Read Pointer
These bits contain the transaction complete FIFO read pointer. This register must only be read
by the CPU / DMA Controller. Writing this register will flush the FIFO write and read pointer.
Bit
+0x03
Read/Write
Initial Value
Bit
+0x04
Read/Write
Initial Value
Bit
+0x05
Read/Write
Initial Value
7
–
R
0
7
–
R
0
7
–
R
0
R/W
–-
R
R
6
0
6
0
6
–
0
R/W
–-
R
R
5
0
5
0
5
–
0
R/W
R/W
R/W
4
0
4
0
4
0
ADDR[6:0]
Atmel AVR XMEGA AU
R/W
R/W
R/W
3
0
3
0
3
0
FIFOWP[4:0]
FIFORP[4:0]
R/W
R/W
R/W
2
0
2
0
2
0
R/W
R/W
R/W
1
0
1
0
1
0
R/W
R/W
R/W
0
0
0
0
0
0
FIFOWP
FIFORP
ADDR
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