ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 285

• Manufacturer Part Number: ATxmega256A3BU
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3BU

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

22.3
22.4
8331A–AVR–07/11
Master Mode
Slave Mode
When the SPI module is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is
overridden according to
from software to have the correct direction according to the application.
Table 22-1.
In master mode, the SPI interface has no automatic control of the SS line. If the SS pin is used,
it must be configured as output and controlled by user software. If the bus consists of several
SPI slaves and/or masters, a SPI master can use general purpose I/O pins to control the SS line
to each of the slaves on the bus.
Writing a byte to the DATA register starts the SPI clock generator and the hardware shifts the
eight bits into the selected slave. After shifting one byte, the SPI clock generator stops and the
SPI interrupt flag is set. The master may continue to shift the next byte by writing new data to the
DATA register, or can signal the end of the transfer by pulling the SS line high. The last incoming
byte will be kept in the buffer register.
If the SS pin is not used and is configured as input, it must be held high to ensure master opera-
tion. If the SS pin is set as input and is being driven low, the SPI module will interpret this as
another master trying to take control of the bus. To avoid bus contention, the master will take the
following action:
In slave mode, the SPI module will remain sleeping with the MISO line tri-stated as long as the
SS pin is driven high. In this state, software may update the contents of the DATA register, but
the data will not be shifted out by incoming clock pulses on the SCK pin until the SS pin is driven
low. If SS is driven low, the slave will start to shift out data on the first SCK clock pulse. When
one byte has been completely shifted, the SPI interrupt flag is set. The slave may continue plac-
ing new data to be sent into the DATA register before reading the incoming data. The last
incoming byte will be kept in the buffer register.
When SS is driven high, the SPI logic is reset, and the SPI slave will not receive any new data.
Any partially received packet in the shift register will be dropped.
As the SS pin is used to signal the start and end of a transfer, it is also useful for doing
packet/byte synchronization, keeping the slave bit counter synchronous with the master clock
generator.
1. The master enters slave mode.
2. The SPI interrupt flag is set.
MOSI
MISO
SCK
Pin
SS
Master Mode
User defined
Input
User defined
User defined
SPI pin override and directions.
Table
22-1. The pins with user-defined direction must be configured
Atmel AVR XMEGA AU
Slave Mode
Input
User defined
Input
Input
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