ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 228

• Manufacturer Part Number: ATxmega256A3BU
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3BU

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.3.10
19.3.11
19.3.12
19.3.13
8331A–AVR–07/11
PER1 - Period Register 1
PER2 - Period Register 2
PER3 - Period Register 3
COMP0 - Compare Register 0
After writing a byte in the PER register, the write (HW/SW) condition for setting OVFIF and the
overflow wake-up condition are disabled for the following two RTC32 clock cycles.
The COMP0, COMP1, COMP2, and COMP3 registers represents the 32-bit value, COMP.
COMP is constantly compared with the counter value (CNT). A compare match will set COMPIF
in the INTFLAGS register, and an interrupt is generated if it is enabled. COMPIF will be set on
next count after a match.
If the COMP value is higher than the PER value, no RTC compare match interrupt requests or
events will be generated.
After writing the high byte of the COMP register, the write condition for setting OVFIF and COM-
PIF, as well as the overflow and compare match wake-up condition, will be disabled for the
following two RTC32 clock cycles.
Bit
+0x08
Read/Write
Initial Value
Bit
+0x09
Read/Write
Reset Value
Bit
+0x0A
Read/Write
Reset Value
Bit
+0x0B
Read/Write
Initial Value
R/W
R/W
R/W
R/W
7
0
7
0
7
0
7
0
R/W
R/W
R/W
R/W
6
0
6
0
6
0
6
0
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
R/W
R/W
R/W
R/W
4
0
4
0
4
0
4
0
PER[23:16]
PER[31:24]
PER[15:8]
PER[7:0]
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
Atmel AVR XMEGA AU
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
PER0
PER1
PER2
PER3
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