ATxmega64A3 Atmel Corporation, ATxmega64A3 Datasheet - Page 120

• Manufacturer Part Number: ATxmega64A3
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

11.7.2
8077H–AVR–12/09
WINCTRL – Window Mode Control Register
• Bit 1 - ENABLE: Watchdog Enable
This bit enables the WDT.
In order to change this bit the CEN bit in
119
Protection mechanism, for detailed description refer to
tection” on page
• Bit 0 - CEN: Watchdog Change Enable
This bit enables the possibility to change the configuration of the
trol Register” on page
one at the same time for the changes to take effect. This bit is protected by the Configuration
Change Protection mechanism, for detailed description refer to
Change Protection” on page
• Bits 7:6 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bits 5:2 - WPER[3:0]: Watchdog Window Mode Timeout Period
These bits determine the closed window period as a number of 1 kHz ULP oscillator cycles in
window mode operation. The typical different closed window periods are found in
The initial values of these bits are set by the Watchdog Window Timeout Period (WDWP) fuses,
and will be loaded at power-on. In normal mode these bits are not in use.
In order to change these bits the WCEN bit must be written to one at the same time. These bits
are protected by the Configuration Change Protection mechanism, for detailed description refer
to
Table 11-2.
Bit
+0x01
Read/Write
(unlocked)
Read/Write
(locked)
Initial Value
(x = fuse)
Section 3.12 ”Configuration Change Protection” on page
WPER[3:0]
must be written to one at the same time. This bit is protected by the Configuration Change
0000
0001
0010
0011
0100
0101
R
R
Watchdog closed window periods
7
0
-
12.
119. When writing a new value to this register, this bit must be written to
R
R
6
0
-
Group Configuration
12.
R/W
R
X
125CLK
250CLK
5
16CLK
32CLK
64CLK
8CLK
”CTRL – Watchdog Timer Control Register” on page
R/W
R
4
X
WPER[3:0]
R/W
R
X
3
Section 3.12 ”Configuration Change Pro-
12.
R/W
Typical closed window periods
2
R
X
”CTRL – Watchdog Timer Con-
Section 3.12 ”Configuration
WEN
R/W
R/W
X
1
0.125 s
16 ms
32 ms
64 ms
0.25 s
8 ms
XMEGA A
WCEN
R/W
R/W
0
0
Table
WINCTRL
11-2.
120