ATxmega64A3 Atmel Corporation, ATxmega64A3 Datasheet - Page 144

• Manufacturer Part Number: ATxmega64A3
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

13.15.3
8077H–AVR–12/09
VPCTRLB - Virtual Port-map Control Register B
• Bit 7:4 - VP1MAP: Virtual Port 1 Mapping
These bits decide which ports should be mapped to Virtual Port 1. The registers DIR, OUT, IN
and INTFLAGS will be mapped. Accessing the virtual port registers is equal to accessing the
actual port registers. See
• Bit 3:0 - VP0MAP: Virtual Port 0 Mapping
These bits decide which ports should be mapped to Virtual Port 0. The registers DIR, OUT, IN
and INTFLAGS will be mapped. Accessing the virtual port registers is equal to accessing the
actual port registers. See
• Bit 7:4 - VP3MAP: Virtual Port 3 Mapping
These bits decide which ports should be mapped to Virtual Port 3. The registers DIR, OUT, IN
and INTFLAGS will be mapped. Accessing the virtual port registers is equal to accessing the
actual port registers. See
• Bit 3:0 - VP2MAP: Virtual Port 2 Mapping
These bits decide which ports should be mapped to Virtual Port 2. The registers DIR, OUT, IN
and INTFLAGS will be mapped. Accessing the virtual port registers is equal to accessing the
actual port registers. See
Table 13-6.
Bit
+0x03
Read/Write
Initial Value
VPnMAP[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
R/W
7
0
Virtual Port mapping.
Group Configuration
PORTA
PORTB
PORTC
PORTD
PORTE
PORTF
PORTG
PORTH
PORTJ
PORTK
PORTL
PORTM
PORTN
R/W
6
0
VP3MAP[3:0]
Table 13-6
Table 13-6
Table 13-6
Table 13-6
R/W
5
0
for configuration.
for configuration.
for configuration.
for configuration.
R/W
4
0
R/W
3
0
Description
PORTA mapped to virtual Port n
PORTB mapped to virtual Port n
PORTC mapped to virtual Port n
PORTD mapped to virtual Port n
PORTE mapped to virtual Port n
PORTF mapped to virtual Port n
PORTG mapped to virtual Port n
PORTH mapped to virtual Port n
PORTJ mapped to virtual Port n
PORTK mapped to virtual Port n
PORTL mapped to virtual Port n
PORTM mapped to virtual Port n
PORTN mapped to virtual Port n
R/W
2
0
VP2MAP[3:0]
R/W
1
0
XMEGA A
R/W
0
0
VPCTRLB
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