ATxmega64A3 Atmel Corporation, ATxmega64A3 Datasheet - Page 193

• Manufacturer Part Number: ATxmega64A3
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

17.3.4
17.3.5
17.3.6
8077H–AVR–12/09
INTFLAGS - RTC Interrupt Flag Register
TEMP - RTC Temporary Register
CNTH - Real Time Counter Register H
• Bits 7:2 - Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 1 - COMPIF: RTC Compare Match Interrupt Flag
This flag is set on the next count after a Compare Match condition occurs. The flag is cleared
automatically when RTC compare match interrupt vector is executed. The flag can also be
cleared by writing a one to its bit location.
• Bit 0 - OVFIF: RTC Overflow Interrupt Flag
This flag is set on the next count after an Overflow condition occurs. The flag is cleared automat-
ically when RTC overflow interrupt vector is executed. The flag can also be cleared by writing a
one to its bit location.
• Bits 7:0 - TEMP[7:0]: Real Time Counter Temporary Register
This register is used for 16-bit access to the counter value, compare value and top value regis-
ters. The low byte of the 16-bit register is stored here when it is written by the CPU. The high
byte of the 16-bit register is stored when low byte is read by the CPU. For more details refer to
”Accessing 16-bits Registers” on page
The CNTH and CNTL register pair represents the 16-bit value CNT. CNT counts positive clock
edges on the prescaled RTC clock. Reading and writing 16-bit values require special attention,
refer to
Due to synchronization between RTC clock and the system clock domains, there is a latency of
two RTC clock cycles from updating the register until this has an effect. Application software
needs to check that the SYNCBUSY flag in the
on page 192
Bit
+0x03
Read/Write
Initial Value
Bit
+0x04
Read/Write
Initial Value
Bit
+0x09
Read/Write
Initial Value
”Accessing 16-bits Registers” on page 12
is cleared before writing to this register.
R/W
R/W
R
7
0
7
0
7
0
-
R/W
R/W
R
6
0
6
0
6
0
-
R/W
R/W
R
5
0
5
0
5
0
-
12.
R/W
R/W
R
4
0
4
0
4
0
-
TEMP[7:0]
CNT[15:8]
”STATUS - Real Time Counter Status Register”
for details.
R/W
R/W
3
R
0
3
0
3
0
-
R/W
R/W
2
R
0
2
0
2
0
-
COMPIF
R/W
R/W
R/W
1
0
1
0
1
0
XMEGA A
OVFIF
R/W
R/W
R/W
0
0
0
0
0
0
INTFLAGS
TEMP
CNTH
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