ATxmega64A3 Atmel Corporation, ATxmega64A3 Datasheet - Page 61

• Manufacturer Part Number: ATxmega64A3
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

5.14.6
5.14.7
5.14.8
8077H–AVR–12/09
TRFCNTL - DMA Channel Block Transfer Count Register L
REPCNT - DMA Channel Repeat Counter Register
SRCADDR2 - DMA Channel Source Address 2
• Bit 7:0 - TRFCNT[15:8]: DMA Channel n Block Transfer Count Register High byte
These bits hold the 8 MSB of the 16-bits block transfer count.
The default value of this register is 0x1. If a user write 0x0 to this register and fire a DMA trigger,
DMA will be doing 0xFFFF transfers.
• Bit 7:0 - TRFCNT[7:0]: DMA Channel n Block Transfer Count Register Low byte
These bits hold the 8 LSB of the 16-bits block transfer count.
The default value of this register is 0x1. If a user write 0x0 to this register and fire a DMA trigger,
DMA will be doing 0xFFFF transfers.
REPCNTcounts how many times a block transfer is performed. For each block transfer this reg-
ister will be decremented.
When repeat mode is enabled (see REPEAT bit in
trol Register” on page
counter is decremented after each block transfer if the DMA has to serve a limited number of
repeated block transfers. When repeat mode is enabled the channel is disabled when REPCNT
reaches zero, and the last block transfer is completed. Unlimited repeat is achieved by setting
this register to zero.
SRCADDR0, SRCADDR1 and SRCADDR2 represents the 24-bit value SRCADDR, which is the
DMA channel source address. SRCADDR2 is the most significant byte in the register.
SRCADDR may be automatically incremented or decremented based on settings in the SRCDIR
bits in
Reading and writing 24-bit values require special attention, for details refer to
”Accessing 24- and 32-bit Registers” on page
Bit
+0x06
Read/Write
Initial Value
Bit
+0x04
Read/Write
Initial Value
Bit
+0x0A
Read/Write
Initial Value
”ADDRCTRL - DMA Channel Address Control Register” on page
R/W
R/W
R/W
7
0
7
1
7
0
57), this register is used to control when the transaction is complete. The
R/W
R/W
R/W
6
0
6
1
6
0
R/W
R/W
R/W
5
0
5
1
5
0
R/W
R/W
R/W
SRCADDR[23:16]
4
0
4
1
4
0
TRFCNT[7:0]
REPCNT[7:0]
12.
R/W
R/W
R/W
”ADDRCTRL - DMA Channel Address Con-
3
1
3
0
3
0
R/W
R/W
R/W
2
0
2
1
2
0
R/W
R/W
R/W
1
1
1
0
1
0
57.
XMEGA A
R/W
R/W
R/W
0
1
0
0
0
0
Section 3.11.1
SRCADDR2
TRFCNTL
REPCNT
61