ATxmega64A3 Atmel Corporation, ATxmega64A3 Datasheet - Page 16

• Manufacturer Part Number: ATxmega64A3
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

3.14.8
3.14.9
8077H–AVR–12/09
SPH - Stack Pointer Register High
SREG - Status Register
Note:
• Bits 7:0 - SP[15:8]: Stack Pointer Register High byte
These bits hold the 8 MSB of the 16-bits Stack Pointer (SP).
The Status Register (SREG) contains information about the result of the most recently executed
arithmetic or logic instruction.
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for interrupts to be enabled. If the Global Interrupt
Enable Register is cleared, none of the interrupts are enabled independent of the individual
interrupt enable settings. The I-bit is not cleared by hardware after an interrupt has occurred.
The I-bit can be set and cleared by the application with the SEI and CLI instructions, as
described in the “Instruction Set Description”.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions Bit Load (BLD) and Bit Store (BST) use the T-bit as source or destina-
tion for the operated bit. A bit from a register in the Register File can be copied into T by the BST
instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD
instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag (H) indicates a Half Carry in some arithmetic operations. Half Carry Is useful
in BCD arithmetic. See the “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N
The Sign bit is always an exclusive or between the Negative Flag N and the Two’s Complement
Overflow Flag V. See the “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag (V) supports two’s complement arithmetics. See the
“Instruction Set Description” for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag (N) indicates a negative result in an arithmetic or logic operation. See the
“Instruction Set Description” for detailed information.
Bit
+0x0E
Read/Write
Initial Value
Bit
+0x0F
Read/Write
Initial Value
1. Refer to specific device datasheets for exact initial values.
(1)
R/W
R/W
7
0
I
0/1
7
R/W
R/W
0/1
T
6
0
6
⊕
V
R/W
R/W
0/1
H
5
5
0
R/W
0/1
R/W
4
S
4
0
SP[15:8]
R/W
0/1
3
R/W
3
V
0
R/W
0/1
2
R/W
2
N
0
R/W
0/1
1
R/W
Z
1
0
XMEGA A
R/W
0/1
0
R/W
C
0
0
SPH
SREG
16