M42800A Atmel Corporation, M42800A Datasheet - Page 162

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Instruction Cycle Timings
6.13
6-20
CP
status
ready
not ready
Coprocessor data operation
Cycle
1
1
2
•
b
Address
pc+8
pc+12
pc+8
pc+8
pc+8
pc+8
pc+12
A coprocessor data operation is a request from the core for the coprocessor to initiate
some action. The action does not have to be completed for some time, but the
coprocessor must commit to doing it before driving CPB LOW.
If the coprocessor is not capable of performing the requested task, it must leave CPA
and CPB HIGH. If it can do the task, but cannot commit right now, it must drive CPA
LOW but leave CPB HIGH until it can commit. The core busy-waits until CPB goes
LOW.
The cycle timings are listed in Table 6-16 where:
•
Coprocessor data operations are not available in Thumb state.
b represents the busy cycles.
Note
nRW
0
0
0
0
0
Copyright © 1994-2001. All rights reserved.
Table 6-16 Coprocessor data operation instruction cycle operations
MAS
[1:0]
2
2
2
2
2
Data
(pc+8)
(pc+8)
-
-
-
nMREQ
0
1
1
1
0
SEQ
0
0
0
0
0
nOPC
0
0
1
1
1
nCPI
0
0
0
0
0
ARM DDI 0029G
CPA
0
0
0
0
0
CPB
0
1
1
1
0