M42800A Atmel Corporation, M42800A Datasheet - Page 95

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI 0029G
Because two memory cycles are required, nWAIT is used to stretch the internal
processor clock. nWAIT does not affect the operation of the data latches. Using this
method, data can be taken from memory as word, halfword, or byte at a time and the
memory can have as many wait states as required. In multi-cycle memory accesses,
nWAIT must be held LOW until the final part is latched.
In the example shown in Figure 3-18, the BL[3:0] signals are driven to value
first cycle so that only the latches on D[15:0] are open. BL[3:0] can be driven to value
the latches on D[31:16] are written with the correct data during the second cycle.
BL[3:0] must be held HIGH during store cycles.
Figure 3-19 on page 3-26 shows a halfword load from single-wait state byte wide
memory. In the figure, each memory access takes two cycles:
•
•
and all of the latches opened. This does not affect the operation of the core because
in the first access:
—
—
—
in the second cycle, the byte for D[15:8] is latched so the halfword on D[15:0] is
correctly read from memory. It does not matter that D[31:16] are unknown
because the core only extracts the halfword that it is interested in.
Note
Copyright © 1994-2001. All rights reserved.
BL[3:0] are driven to
the correct data is latched from D[7:0]
unknown data is latched from D[31:8].
D[31:16]
nMREQ
A[31:0]
D[15:0]
BL[3:0]
nWAIT
MCLK
SEQ
APE
0x3
Figure 3-18 Memory access
0xC
Memory Interface
in the
3-25