SAM3N4A Atmel Corporation, SAM3N4A Datasheet - Page 188

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SAM3N4A

Manufacturer Part Number
SAM3N4A
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM3N4A

Flash (kbytes)
256 Kbytes
Pin Count
48
Max. Operating Frequency
48 MHz
Cpu
Cortex-M3
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Quadrature Decoder Channels
2
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
2
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
24
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
10.21.13 Memory Management Fault Address Register
• ADDRESS
When the MMARVALID bit of the MMFSR is set to 1, this field holds the address of the location that generated the memory
management fault
When an unaligned access faults, the address is the actual address that faulted. Because a single read or write instruction
can be split into multiple aligned accesses, the fault address can be any address in the range of the requested access size.
Flags in the MMFSR indicate the cause of the fault, and whether the value in the MMFAR is valid. See
ment Fault Status Register” on page
188
31
23
15
7
SAM3N
30
22
14
6
The MMFAR contains the address of the location that generated a memory management fault.
See the register summary in
182.
29
21
13
5
28
20
12
4
Table 10-30 on page 164
ADDRESS
ADDRESS
ADDRESS
ADDRESS
27
19
11
3
for its attributes. The bit assignments are:
26
18
10
2
25
17
9
1
11011A–ATARM–04-Oct-10
“Memory Manage-
24
16
8
0

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