SAM3N4A Atmel Corporation, SAM3N4A Datasheet - Page 661

• Manufacturer Part Number: SAM3N4A
• Manufacturer: Atmel Corporation

Specifications of SAM3N4A

• Flash (kbytes): 256 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 48 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Quadrature Decoder Channels: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 2
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 24
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

33.7.2
Name:
Address:
Access:
This register can only be written if the WPEN bit is cleared in
• TRGEN: Trigger Enable
• TRGSEL: Trigger Selection
• LOWRES: Resolution
• SLEEP: Sleep Mode
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10
FREERUN
Value
Value
USEQ
Value
Value
31
23
15
0
1
0
1
0
1
2
3
4
5
6
7
0
1
–
7
ADC Mode Register
NORMAL
SLEEP
Name
FWUP
ADC_TRIG0
ADC_TRIG1
ADC_TRIG2
ADC_TRIG3
ADC_TRIG4
ADC_TRIG5
ADC_TRIG6
30
22
14
ADC_MR
0x40038004
Read-write
–
–
6
BITS_10
BITS_8
Name
Name
Name
DIS
EN
–
Description
Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions
Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions
SLEEP
29
21
13
–
–
5
Hardware triggers are disabled. Starting a conversion is only possible by software.
Description
Hardware trigger selected by TRGSEL field is enabled.
Description
10-bit resolution
8-bit resolution
Description
External trigger
TIO Output of the Timer Counter Channel 0
TIO Output of the Timer Counter Channel 1
TIO Output of the Timer Counter Channel 2
Reserved
Reserved
Reserved
Reserved
LOWRES
28
20
12
–
–
4
PRESCAL
“ADC Write Protect Mode Register” on page
27
19
11
3
TRGSEL
26
18
10
2
TRACKTIM
STARTUP
25
17
9
1
677.
SAM3N
SAM3N
TRGEN
24
16
8
0
661
661