SAM3N4A Atmel Corporation, SAM3N4A Datasheet - Page 259

• Manufacturer Part Number: SAM3N4A
• Manufacturer: Atmel Corporation

Specifications of SAM3N4A

• Flash (kbytes): 256 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 48 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Quadrature Decoder Channels: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 2
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 24
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

16.4.4
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SAM3N
SAM3N
Supply Monitor
The Supply Controller embeds a supply monitor which is located in the VDDIO Power Supply
and which monitors VDDIO power supply.
The supply monitor can be used to prevent the processor from falling into an unpredictable state
if the Main power supply drops below a certain level.
The threshold of the supply monitor is programmable. It can be selected from 1.9V to 3.4V by
steps of 100 mV. This threshold is programmed in the SMTH field of the Supply Controller Sup-
ply Monitor Mode Register (SUPC_SMMR).
The supply monitor can also be enabled during one slow clock period on every one of either 32,
256 or 2048 slow clock periods, according to the choice of the user. This can be configured by
programming the SMSMPL field in SUPC_SMMR.
Enabling the supply monitor for such reduced times allows to divide the typical supply monitor
power consumption respectively by factors of 32, 256 or 2048, if the user does not need a con-
tinuous monitoring of the VDDIO power supply.
A supply monitor detection can either generate a reset of the core power supply or a wake up of
the core power supply. Generating a core reset when a supply monitor detection occurs is
enabled by writing the SMRSTEN bit to 1 in SUPC_SMMR.
Waking up the core power supply when a supply monitor detection occurs can be enabled by
programming the SMEN bit to 1 in the Supply Controller Wake Up Mode Register
(SUPC_WUMR).
The Supply Controller provides two status bits in the Supply Controller Status Register for the
supply monitor which allows to determine whether the last wake up was due to the supply
monitor:
The SMS bit can generate an interrupt if the SMIEN bit is set to 1 in the Supply Controller Supply
Monitor Mode Register (SUPC_SMMR).
• The SMOS bit provides real time information, which is updated at each measurement cycle
• The SMS bit provides saved information and shows a supply monitor detection has occurred
or updated at each Slow Clock cycle, if the measurement is continuous.
since the last read of SUPC_SR.
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10