SAM3S16C Atmel Corporation, SAM3S16C Datasheet - Page 45

• Manufacturer Part Number: SAM3S16C
• Manufacturer: Atmel Corporation

Specifications of SAM3S16C

• Flash (kbytes): 1024 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 100 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 39
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

12.2.4
12.2.4.1
12.2.4.2
12.2.4.3
12.2.4.4
12.3
12.3.1
12.3.1.1
12.3.1.2
12.3.1.3
11117B–ATARM–18-Oct-11
Programmers model
Cortex-M3 core peripherals
Processor mode and privilege levels for software execution
Nested Vectored Interrupt Controller
System control block
System timer
Memory protection unit
Thread mode
Handler mode
Unprivileged
These are:
The Nested Vectored Interrupt Controller (NVIC) is an embedded interrupt controller that sup-
ports low latency interrupt processing.
The System control block (SCB) is the programmers model interface to the processor. It pro-
vides system implementation information and system control, including configuration, control,
and reporting of system exceptions.
The system timer, SysTick, is a 24-bit count-down timer. Use this as a Real Time Operating Sys-
tem (RTOS) tick timer or as a simple counter.
The Memory protection unit (MPU) improves system reliability by defining the memory attributes
for different memory regions. It provides up to eight different regions, and an optional predefined
background region.
This section describes the Cortex-M3 programmers model. In addition to the individual core reg-
ister descriptions, it contains information about the processor modes and privilege levels for
software execution and stacks.
The processor modes are:
Used to execute application software. The processor enters Thread mode when it comes out of
reset.
Used to handle exceptions. The processor returns to Thread mode when it has finished excep-
tion processing.
The privilege levels for software execution are:
The software:
• deterministic, high-performance interrupt handling for time-critical applications
• Memory Protection Unit (MPU) for safety-critical applications
• extensive debug and trace capabilities:
• has limited access to the MSR and MRS instructions, and cannot use the CPS instruction
– Serial Wire Debug and Serial Wire Trace reduce the number of pins required for
debugging and tracing.
SAM3S16
3