SAM3S16C Atmel Corporation, SAM3S16C Datasheet - Page 65
SAM3S16C
Manufacturer Part Number
SAM3S16C
Description
Manufacturer
Atmel Corporation
Datasheet
1.SAM3S16C.pdf
(1130 pages)
Specifications of SAM3S16C
Flash (kbytes)
1024 Kbytes
Pin Count
100
Max. Operating Frequency
100 MHz
Cpu
Cortex-M3
# Of Touch Channels
39
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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12.4.6.1
12.4.7
12.4.7.1
12.4.7.2
11117B–ATARM–18-Oct-11
Synchronization primitives
Little-endian format
A Load-Exclusive instruction
A Store-Exclusive instruction
In little-endian format, the processor stores the least significant byte of a word at the lowest-
numbered byte, and the most significant byte at the highest-numbered byte. For example:
The Cortex-M3 instruction set includes pairs of synchronization primitives. These provide a non-
blocking mechanism that a thread or process can use to obtain exclusive access to a memory
location. Software can use them to perform a guaranteed read-modify-write memory update
sequence, or for a semaphore mechanism.
A pair of synchronization primitives comprises:
Used to read the value of a memory location, requesting exclusive access to that location.
Used to attempt to write to the same memory location, returning a status bit to a register. If this
bit is:
0: it indicates that the thread or process gained exclusive access to the memory, and the write
succeeds,
1: it indicates that the thread or process did not gain exclusive access to the memory, and no
write is performed,
The pairs of Load-Exclusive and Store-Exclusive instructions are:
Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive
instruction.
To perform a guaranteed read-modify-write of a memory location, software must:
Address A
• the word instructions LDREX and STREX
• the halfword instructions LDREXH and STREXH
• the byte instructions LDREXB and STREXB.
• Use a Load-Exclusive instruction to read the value of the location.
• Update the value, as required.
• Use a Store-Exclusive instruction to attempt to write the new value back to the memory
location, and tests the returned status bit. If this bit is:
0: The read-modify-write completed successfully,
A+1
A+2
A+3
7
Memory
B0
B1
B2
B3
0
lsbyte
msbyte
31
B3
24 23
B2
Register
16 15
B1
8 7
B0
0
SAM3S16
23
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