SAM3S16C Atmel Corporation, SAM3S16C Datasheet - Page 906

• Manufacturer Part Number: SAM3S16C
• Manufacturer: Atmel Corporation

Specifications of SAM3S16C

• Flash (kbytes): 1024 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 100 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 39
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

38.7.9
Name:
Address:
Access:
This register can only be written if the bits WPSWS2 and WPHWS2 are cleared in
page
• SYNCx: Synchronous Channel x
0 = Channel x is not a synchronous channel.
1 = Channel x is a synchronous channel.
• UPDM: Synchronous Channels Update Mode
Notes:
• PTRM: PDC Transfer Request Mode
• PTRCS: PDC Transfer Request Comparison Selection
Selection of the comparison used to set the flag WRDY and the corresponding PDC transfer request.
864
864
Value
0
1
2
3
UPDM
887.
31
23
15
–
–
7
–
0
1
2
1. The update occurs at the beginning of the next PWM period, when the UPDULOCK bit in
2. The update occurs when the Update Period is elapsed.
SAM3S16
SAM3S16
PWM Sync Channels Mode Register
Control Register”
PWM_SCM
0x40020020
Read-write
MODE0
MODE1
MODE2
Name
–
PTRCS
PTRM
30
22
14
–
–
6
–
0
1
x
x
is set.
Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels
Reserved
Manual write of double buffer registers and manual update of synchronous channels
Manual write of double buffer registers and automatic update of synchronous channels
The WRDY flag in
are never set to 1.
The WRDY flag in
update period is elapsed, the PDC transfer request is never set to 1.
The WRDY flag in
are set to 1 as soon as the update period is elapsed.
The WRDY flag in
are set to 1 as soon as the selected comparison matches.
WRDY Flag and PDC Transfer Request
29
21
13
–
–
5
–
PTRM
“PWM Interrupt Status Register 2” on page 871
“PWM Interrupt Status Register 2” on page 871
“PWM Interrupt Status Register 2” on page 871
“PWM Interrupt Status Register 2” on page 871
28
20
12
–
–
4
–
SYNC3
27
19
11
–
–
–
3
Description
SYNC2
“PWM Write Protect Status Register” on
26
18
10
–
–
–
2
“PWM Sync Channels Update
and the PDC transfer request
is set to 1 as soon as the
and the PDC transfer request
and the PDC transfer request
SYNC1
25
17
–
9
–
1
11117B–ATARM–18-Oct-11
11117B–ATARM–18-Oct-11
UPDM
(1)
(2)
SYNC0
24
16
–
8
–
0
(2)