SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 367
SAM3U2C
Manufacturer Part Number
SAM3U2C
Description
Manufacturer
Atmel Corporation
Specifications of SAM3U2C
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
96 MHz
Cpu
Cortex-M3
# Of Touch Channels
28
Hardware Qtouch Acquisition
No
Max I/o Pins
57
Ext Interrupts
57
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
4
Twi (i2c)
1
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
36
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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25.12 Automatic Wait States
25.12.1
Figure 25-13. Chip Select Wait State between a Read Access on NCS0 and a Write Access on NCS2
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11
Chip Select Wait States
NBS0, NBS1,
D[15:0]
A[23:2]
A0,A1
NCS0
NCS2
NWE
MCK
NRD
One bit is dedicated to enable/disable NAND Flash scrambling and one bit is dedicated
enable/disable scrambling the off chip SRAM. When at least one external SRAM is scrambled,
the SMSC field must be set in the SMC_OCMS register.
When multiple chip selects (external SRAM) are handled, it is possible to configure the scram-
bling function per chip select using the OCMS field in the SMC_TIMINGS registers.
To scramble the NAND Flash contents, the SRSE field must be set in the SMC_OCMS register.
When NAND Flash memory content is scrambled, the on-chip SRAM page buffer associated for
the transfer is also scrambled.
Under certain circumstances, the SMC automatically inserts idle cycles between accesses to
avoid bus contention or operation conflict.
The SMC always inserts an idle cycle between 2 transfers on separate chip selects. This idle
cycle ensures that there is no bus contention between the de-activation of one device and the
activation of the next one.
During chip select wait state, all control lines are turned inactive: NBS0 to NBS1, NWR0 to
NWR1, NCS[0..3], and NRD lines. They are all set to 1.
Figure 25-13
Select 2.
NRD_CYCLE
illustrates a chip select wait state between access on Chip Select 0 and Chip
Read to Write
Wait State
Chip Select
Wait State
NWE_CYCLE
SAM3U Series
SAM3U Series
367
367
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