SAM3U4E Atmel Corporation, SAM3U4E Datasheet - Page 1063
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SAM3U4E
Manufacturer Part Number
SAM3U4E
Description
Manufacturer
Atmel Corporation
Specifications of SAM3U4E
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
96 MHz
Cpu
Cortex-M3
# Of Touch Channels
57
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
5
Twi (i2c)
2
Uart
5
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
50
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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41. 12-bit Analog-to-Digital Converter (ADC12B)
41.1
41.2
Figure 41-1. Analog-to-Digital Converter Block Diagram
6430E–ATARM–29-Aug-11
Analog
Inputs
AD12BVREF
AD12BTRG
VDDANA
AD12B0
AD12B1
AD12Bn
Description
Block Diagram
GND
PIO
The ADC12B is based on a Cyclic Pipeline 12-bit Analog-to-Digital Converter (ADC12B).
It also integrates an 8-to-1 analog multiplexer, making possible the analog-to-digital conversions
of 8 analog lines. The conversions extend from 0V to AD12BVREF.
The ADC12B supports a 10-bit or 12-bit resolution mode, and conversion results are reported in
a common register for all channels, as well as in a channel-dedicated register. Software trigger,
external trigger on rising edge of the AD12BTRG pin, internal triggers from Timer Counter out-
put(s) or PWM Event lines are configurable.
The ADC12B also integrates a Sleep Mode and a conversion sequencer and connects with a
PDC channel. These features reduce both power consumption and processor intervention.
This ADC12B has a selectable single-ended or fully differential input and benefits from a 2-bit
programmable gain. A whole set of reference voltage is generated internally from a single exter-
nal reference voltage node that may be equal to the analog supply voltage. An external
decoupling capacitance is required for noise filtering.
A digital error correction circuit based on the multi-bit redundant signed digit (RSD) algorithm is
employed in order to reduce INL and DNL errors.
Finally, the user can configure ADC12B timings, such as Startup Time and Sample & Hold Time.
Selection
Channels
Trigger
Counter
Timer
IN+
IN-
OFFSET
S/H
ADC12B
PGA
12-bit Analog-to-Digital
Cyclic Pipeline
Converter
Interface
Control
Logic
User
ADC12B Interrupt
PDC
SAM3U Series
NVIC
Peripheral Bridge
AHB
APB
1063
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