SAM3U4E Atmel Corporation, SAM3U4E Datasheet - Page 72
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SAM3U4E
Manufacturer Part Number
SAM3U4E
Description
Manufacturer
Atmel Corporation
Specifications of SAM3U4E
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
96 MHz
Cpu
Cortex-M3
# Of Touch Channels
57
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
5
Twi (i2c)
2
Uart
5
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
50
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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13.4.5
72
SAM3U Series
Bit-banding
Memory accesses to Strongly-ordered memory, such as the system control block, do not require
the use of DMB instructions.
A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region.
The bit-band regions occupy the lowest 1MB of the SRAM and peripheral memory regions.
The memory map has two 32MB alias regions that map to two 1MB bit-band regions:
Table 13-6.
Address
range
0x20000000-
0x200FFFFF
0x22000000-
0x23FFFFFF
• Vector table. If the program changes an entry in the vector table, and then enables the
• Self-modifying code. If a program contains self-modifying code, use an ISB instruction
• Memory map switching. If the system contains a memory map switching mechanism, use a
• Dynamic exception priority change. When an exception priority has to change when the
• Using a semaphore in multi-master system. If the system contains more than one bus
• accesses to the 32MB SRAM alias region map to the 1MB SRAM bit-band region, as shown
• accesses to the 32MB peripheral alias region map to the 1MB peripheral bit-band region, as
corresponding exception, use a DMB instruction between the operations. This ensures that if
the exception is taken immediately after being enabled the processor uses the new exception
vector.
immediately after the code modification in the program. This ensures subsequent instruction
execution uses the updated program.
DSB instruction after switching the memory map in the program. This ensures subsequent
instruction execution uses the updated memory map.
exception is pending or active, use DSB instructions after the change. This ensures the
change takes effect on completion of the DSB instruction.
master, for example, if another processor is present in the system, each processor must use
a DMB instruction after any semaphore instructions, to ensure other bus masters see the
memory transactions in the order in which they were executed.
in
shown in
Table 13-6
– Use an ISB instruction to ensure the new MPU setting takes effect immediately after
programming the MPU region or regions, if the MPU configuration code was
accessed using a branch or call. If the MPU configuration code is entered using
exception mechanisms, then an ISB instruction is not required.
Table
SRAM memory bit-banding regions
Memory
region
SRAM bit-band
region
SRAM bit-band alias
13-7.
Instruction and data accesses
Direct accesses to this memory range behave as SRAM
memory accesses, but this region is also bit addressable
through bit-band alias.
Data accesses to this region are remapped to bit band
region. A write operation is performed as read-modify-write.
Instruction accesses are not remapped.
6430E–ATARM–29-Aug-11
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