SAM3U4E Atmel Corporation, SAM3U4E Datasheet - Page 132
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SAM3U4E
Manufacturer Part Number
SAM3U4E
Description
Manufacturer
Atmel Corporation
Specifications of SAM3U4E
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
96 MHz
Cpu
Cortex-M3
# Of Touch Channels
57
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
5
Twi (i2c)
2
Uart
5
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
50
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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13.12.9
13.12.9.1
13.12.9.2
13.12.9.3
13.12.9.4
13.12.9.5
132
TST
TEQEQ
SAM3U Series
TST and TEQ
Syntax
Operation
Restrictions
Condition flags
Examples
R0, #0x3F8
R10, R9
Test bits and Test Equivalence.
where:
cond
Rn
Operand2
details of the options.
These instructions test the value in a register against Operand2. They update the condition flags
based on the result, but do not write the result to a register.
The TST instruction performs a bitwise AND operation on the value in Rn and the value of
Operand2. This is the same as the ANDS instruction, except that it discards the result.
To test whether a bit of Rn is 0 or 1, use the TST instruction with an Operand2 constant that has
that bit set to 1 and all other bits cleared to 0.
The TEQ instruction performs a bitwise Exclusive OR operation on the value in Rn and the value
of Operand2. This is the same as the EORS instruction, except that it discards the result.
Use the TEQ instruction to test if two values are equal without affecting the V or C flags.
TEQ is also useful for testing the sign of a value. After the comparison, the N flag is the logical
Exclusive OR of the sign bits of the two operands.
Do not use SP and do not use PC
These instructions:
• update the N and Z flags according to the result
• can update the C flag during the calculation of Operand2, see
• do not affect the V flag.
page 94
TST{cond} Rn, Operand2
TEQ{cond} Rn, Operand2
; Perform bitwise AND of R0 value to 0x3F8,
; APSR is updated but result is discarded
; Conditionally test if value in R10 is equal to
; value in R9, APSR is updated but result is discarded
is an optional condition code, see
is the register holding the first operand.
is a flexible second operand. See
.
“Conditional execution” on page
“Flexible second operand” on page 94
“Flexible second operand” on
6430E–ATARM–29-Aug-11
98.
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