SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 108
SAM9263
Manufacturer Part Number
SAM9263
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.SAM9260.pdf
(290 pages)
4.SAM9261.pdf
(248 pages)
5.SAM9263.pdf
(1109 pages)
6.SAM9263.pdf
(51 pages)
Specifications of SAM9263
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Can
1
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
NO
External Bus Interface
2
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- SAM9260 PDF datasheet #3
- SAM9261 PDF datasheet #4
- SAM9263 PDF datasheet #5
- SAM9263 PDF datasheet #6
- Current page: 108 of 290
- Download datasheet (5Mb)
CLK
CLKEN
DnMREQ,
DSEQ,
DMORE,
DnSPEC
Address class
signals
Memory Interface
4.12.1
4-32
Withdrawal of memory requests in waited cycles
during a waited cycle. In addition, the ARM9E-S can alter the request for a subsequent
memory cycle during a waited (CLKEN LOW) cycle. See Withdrawal of memory
requests in waited cycles.
The ARM9E-S can alter the value of the memory request and address signals during
cycles in which CLKEN is LOW. This is done to improve the worst case interrupt
latency of ARM9E-S systems. For example, a pending memory request can be
withdrawn if the core is about to take an interrupt and the access is unnecessary.
The ARM9E-S does not alter or withdraw any access to which it is committed. An
access is said to be committed when the address and request signals are sampled on the
rising edge of CLK when CLKEN is HIGH.
The ARM9E-S only attempts to alter or withdraw an uncommitted access during the
extended (or waited) bus cycle of a previous access. Alteration of the next memory
request during a waited bus cycle is shown in Figure 4-13.
This behavior affects the IA, InMREQ, ISEQ, DA, DnMREQ, DSEQ, DMORE, and
DnSPEC outputs of the ARM9E-S.
Request 1
Address 1
N cycle
Note
Copyright © 2000 ARM Limited. All rights reserved.
Figure 4-13 Alteration of next memory request during waited bus cycle
Ignored
Ignored
First bus cycle
Ignored
Ignored
Internal cycle
Second bus cycle
ARM DDI 0165B
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