SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 152
SAM9263
Manufacturer Part Number
SAM9263
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.SAM9260.pdf
(290 pages)
4.SAM9261.pdf
(248 pages)
5.SAM9263.pdf
(1109 pages)
6.SAM9263.pdf
(51 pages)
Specifications of SAM9263
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Can
1
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
NO
External Bus Interface
2
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- SAM9260 PDF datasheet #3
- SAM9261 PDF datasheet #4
- SAM9263 PDF datasheet #5
- SAM9263 PDF datasheet #6
- Current page: 152 of 290
- Download datasheet (5Mb)
Debug Interface and EmbeddedICE-RT
7.6
7.6.1
7-14
ARM9E-S core clock domains
Clocks and synchronization
Multi-ICE
interface
pads
The ARM9E-S has a single clock, CLK, that is qualified by two clock enables:
•
•
During normal operation, CLKEN conditions CLK to clock the core. When the
ARM9E-S is in debug state, DBGTCKEN conditions CLK to clock the core.
If the system and test clocks are asynchronous, they must be synchronized externally to
the ARM9E-S macrocell. The ARM Multi-ICE debug agent directly supports one or
more cores within an ASIC design. To synchronize off-chip debug clocking with the
ARM9E-S macrocell requires a three-stage synchronizer. The off-chip device (for
example, Multi-ICE) issues a TCK signal, and waits for the RTCK (Returned TCK)
signal to come back. Synchronization is maintained because the off-chip device does
not progress to the next TCK until after RTCK is received. Figure 7-7 shows this
synchronization.
TDO
RTCK
TCK
TMS
TDI
CLKEN controls access to the memory system
DBGTCKEN controls debug operations.
CLK
Copyright © 2000 ARM Limited. All rights reserved.
D
Q
TCK synchronizer
D
Q
D
Q
Figure 7-7 Clock synchronization
CLK
Input sample and hold
D
EN
Q
CLK
D
EN
Q
ARM DDI 0165B
DBGTCKEN
DBGTDO
DBGTMS
DBGTDI
CLK
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