SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 113
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SAM9263
Manufacturer Part Number
SAM9263
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.SAM9260.pdf
(290 pages)
4.SAM9261.pdf
(248 pages)
5.SAM9263.pdf
(1109 pages)
6.SAM9263.pdf
(51 pages)
Specifications of SAM9263
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Can
1
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
NO
External Bus Interface
2
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- SAM9260 PDF datasheet #3
- SAM9261 PDF datasheet #4
- SAM9263 PDF datasheet #5
- SAM9263 PDF datasheet #6
- Current page: 113 of 290
- Download datasheet (5Mb)
5.2.4
ARM DDI 0165B
Interrupt registers
Example approaches are:
•
•
•
Before use, the nFIQ and nIRQ inputs are registered internally to the ARM9E-S. To
improve interrupt latency, the registers are not conditioned by CLKEN, and run freely,
off the system clock, CLK. Internally, the ARM9E-S can use the registered nFIQ or
nIRQ status to prepare for interrupt entry, even if the rest of the core is being waited by
CLKEN. The registered interrupt signals can only update if CLK is running. Because
of this, the best interrupt latency can only be achieved if CLK is not stopped. This
requirement is counteracted by power saving features of a system (for instance,
stopping CLK while waiting for a slow memory device, or a power-down mode where
CLK is stopped). In systems like this, you can still achieve the best interrupt latency if
you replace the final disabled CLK cycle with one waited (CLKEN = 0) cycle.
Figure 5-2 shows a system where CLK is stopped by external clock-gating for a
number of cycles.
Figure 5-3 on page 5-6 shows a system which achieves most of the power saving
benefits of the system shown in Figure 5-2, while at the same time achieving best
interrupt latency.
Analyze the system and ensure enough instructions separate the instruction that
removes the interrupt and the instruction that re-enables interrupts on the
ARM9E-S.
Have a software polling mechanism that reads back a status bit from the system
interrupt controller until it indicates that the interrupt has been removed before
re-enabling interrupts.
Have a hardware system that stalls the ARM9E-S until the interrupt has been
removed.
Copyright © 2000 ARM Limited. All rights reserved.
Figure 5-2 Stopping CLK for power saving
Interrupts
5-5
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