SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 91
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SAM9263
Manufacturer Part Number
SAM9263
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.SAM9260.pdf
(290 pages)
4.SAM9261.pdf
(248 pages)
5.SAM9263.pdf
(1109 pages)
6.SAM9263.pdf
(51 pages)
Specifications of SAM9263
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Can
1
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
NO
External Bus Interface
2
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- SAM9260 PDF datasheet #3
- SAM9261 PDF datasheet #4
- SAM9263 PDF datasheet #5
- SAM9263 PDF datasheet #6
- Current page: 91 of 290
- Download datasheet (5Mb)
4.8
4.8.1
4.8.2
ARM DDI 0165B
Data interface addressing signals
DA[31:0]
DnRW
The address class signals are:
•
•
•
•
•
•
DA[31:0] is the 32-bit address bus that specifies the address for the transfer. All
addresses are byte addresses, so a burst of word accesses results in the address bus
incrementing by 4 for each cycle.
The address bus provides 4GB of linear addressing space. When a word access is
signaled the memory system must ignore the bottom two bits, DA[1:0], and when a
halfword access is signaled the memory system must ignore the bottom bit, DA[0].
DnRW specifies the direction of the transfer. DnRW indicates an ARM9E-S write
cycle when HIGH, and an ARM9E-S read cycle when LOW. A burst of S cycles is
always either a read burst, or a write burst, because the direction cannot be changed in
the middle of a burst.
You must not initiate writes to memory purely on the basis of DnRW. You must use the
status of the data interface request signals to condition writes to memory. See Data
interface cycle types on page 4-24 for more details.
DA[31:0]
DnRW
DMAS[1:0] on page 4-16
DnTRANS on page 4-16
DLOCK on page 4-17
DnM[4:0] on page 4-17.
Note
Copyright © 2000 ARM Limited. All rights reserved.
Memory Interface
4-15
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