SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 118
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SAM9263
Manufacturer Part Number
SAM9263
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.SAM9260.pdf
(290 pages)
4.SAM9261.pdf
(248 pages)
5.SAM9263.pdf
(1109 pages)
6.SAM9263.pdf
(51 pages)
Specifications of SAM9263
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Can
1
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
NO
External Bus Interface
2
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- SAM9260 PDF datasheet #3
- SAM9261 PDF datasheet #4
- SAM9263 PDF datasheet #5
- SAM9263 PDF datasheet #6
- Current page: 118 of 290
- Download datasheet (5Mb)
ARM9E-S Coprocessor Interface
6.1
6.1.1
6.1.2
6-2
About the coprocessor interface
Coprocessor pipeline operates in step with the ARM9E-S
Coprocessor pipeline one cycle behind the ARM9E-S
The ARM9E-S supports the connection of coprocessors. All types of ARM
coprocessors are supported. Coprocessors determine the instructions they need to
execute using a pipeline follower in the coprocessor. As each instruction arrives from
memory, it enters both the ARM pipeline and the coprocessor pipeline. The coprocessor
determines when an instruction is being fetched by the ARM9E-S, so that the
instruction can be loaded into the coprocessor, and the pipeline follower advanced.
The coprocessor can be run either in step with the ARM9E-S pipeline, or one cycle
behind, depending on the timing priorities. The implications of the two approaches are
discussed in:
•
•
In this case, the pipeline follower inside the coprocessor matches that of the ARM9E-S
exactly. This complicates the timing of key signals such as the INSTR and CLKEN
inputs, because these now become more heavily loaded and therefore incur more delay.
For this reason, this method is only recommended for tightly integrated coprocessors
such as CP15, the system coprocessor.
This method is recommended for external coprocessors. A coprocessor interface block
pipelines the instruction and control signals so that the loading is reduced on these
critical signals. This means that the pipeline in the coprocessor operates one cycle
behind the ARM9E-S pipeline. The disadvantage of this is that outputs of the
coprocessor are still expected in the correct pipeline stage, as seen from the ARM9E-S.
The most critical signal in this situation is likely to be CHSD[1:0], the coprocessor
decode handshake signal. This must return the availability of the coprocessor by the end
of the decode cycle, as seen by the ARM9E-S. This is equivalent to the fetch cycle of
the coprocessor pipeline, and therefore there is not much time to generate this signal.
This means that the design might have to insert wait states for external coprocessor
accesses.
There are three classes of coprocessor instructions:
•
•
•
Coprocessor pipeline operates in step with the ARM9E-S
Coprocessor pipeline one cycle behind the ARM9E-S.
LDC
MCR
CDP
Copyright © 2000 ARM Limited. All rights reserved.
/
/
.
STC
MRC
ARM DDI 0165B
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