SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 102
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SAM9263
Manufacturer Part Number
SAM9263
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.SAM9260.pdf
(290 pages)
4.SAM9261.pdf
(248 pages)
5.SAM9263.pdf
(1109 pages)
6.SAM9263.pdf
(51 pages)
Specifications of SAM9263
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Can
1
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
NO
External Bus Interface
2
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- SAM9260 PDF datasheet #3
- SAM9261 PDF datasheet #4
- SAM9263 PDF datasheet #5
- SAM9263 PDF datasheet #6
- Current page: 102 of 284
- Download datasheet (2Mb)
Memory Interface
3.9
3-32
Privileged mode access
ARM Limited usually recommends that if only privileged mode access is required from
a memory system then you are advised to use the nTRANS pin on the core. This signal
distinguishes between User and privileged accesses.
The reason that this is recommended is that if the Operating System (OS) accesses
memory on behalf of the current application then it must perform these accesses in User
mode. This is achieved using the LDRT and STRT instructions that set nTRANS
appropriately.
This measure avoids the possibility of a hacker deliberately passing an invalid pointer
to an OS and getting the OS to access this memory with privileged access. This
technique could otherwise be used by a hacker to enable the user application to access
any memory locations such as I/O space.
The least significant five bits of the CPSR are also output from the core as inverted
signals, nM[4:0]. These indicate the current processor mode as listed in Table 3-8.
The only time to use the nM[4:0] signals is for diagnostic and debug purposes.
Note
Copyright © 1994-2001. All rights reserved.
Table 3-8 Use of nM[4:0] to indicate current processor mode
M[4:0]
10000
10001
10010
10011
10111
11011
11111
nM[4:0]
01111
01110
01101
01100
01000
00100
00000
ARM DDI 0029G
Mode
User
FIQ
IRQ
Supervisor
Abort
Undefined
System
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