SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 131
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SAM9263
Manufacturer Part Number
SAM9263
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.SAM9260.pdf
(290 pages)
4.SAM9261.pdf
(248 pages)
5.SAM9263.pdf
(1109 pages)
6.SAM9263.pdf
(51 pages)
Specifications of SAM9263
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Can
1
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
NO
External Bus Interface
2
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- SAM9260 PDF datasheet #3
- SAM9261 PDF datasheet #4
- SAM9263 PDF datasheet #5
- SAM9263 PDF datasheet #6
- Current page: 131 of 284
- Download datasheet (2Mb)
5.3.2
ARM DDI 0029G
Action of the processor in debug state
When the ARM7TDMI core enters debug state, the core forces nMREQ and SEQ to
indicate internal cycles. This action allows the rest of the memory system to ignore the
core and to function as normal. Because the rest of the system continues to operate, the
ARM7TDMI is forced to ignore aborts and interrupts.
The system must not change the BIGEND signal during debug because the debugger is
unaware that the core has been reconfigured.
nRESET must be held stable during debug because resetting the core while debugging
causes the debugger to lose track of the core.
When the system applies reset to the ARM7TDMI processor, with nRESET driven
LOW, the processor state changes with the debugger unaware that the core has reset.
When instructions are executed in debug state, all memory interface outputs, except
nMREQ and SEQ, change asynchronously to the memory system. For example, every
time a new instruction is scanned into the pipeline, the address bus changes. Although
this is asynchronous it does not affect the system, as nMREQ and SEQ are forced to
indicate internal cycles regardless of what the rest of the core is doing. The memory
controller must be designed to ensure that this asynchronous behavior does not affect
the rest of the system.
Copyright © 1994-2001. All rights reserved.
Debug Interface
5-9
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