AD9434 Analog Devices, AD9434 Datasheet
AD9434
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AD9434 Summary of contents
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... Standard serial port interface supports various product functions, such as data formatting, power-down, gain adjust, and output test pattern generation. 5. The AD9434 is pin compatible with the AD9230, and can be substituted in many applications with minimal design changes. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. ...
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... Power Dissipation and Power-Down Mode ........................... 21 Digital Outputs ........................................................................... 21 Timing ......................................................................................... 22 VREF ............................................................................................ 22 AD9434 Configuration Using the SPI ..................................... 22 Using the AD9434 to Replace the AD9230............................. 23 Hardware Interface ..................................................................... 23 Configuration Without the SPI ................................................ 23 Memory Map .................................................................................. 25 Reading the Memory Map Table .............................................. 25 ...
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... MHz sine input at rated sample rate. AVDD DRVDD 4 Single data rate mode; this is the default mode of the AD9434. 5 Double data rate mode; user-programmable feature. See the Memory Map section. = +85° −1.0 dBFS, full scale = 1.5 V, unless otherwise noted. ...
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... Full 75 25°C 79 25°C 78 25°C −90 25°C −90 25°C −91 Full 25°C −83 25°C −82 25°C −85 25°C 1 Rev Page AD9434-500 Max Min Typ Max 65.9 65.9 65.8 64.5 65.2 63.5 65.9 65.8 65.8 64.4 64.8 62.9 10.7 10.6 10.6 10.5 10.2 −93 −91 −87 −75 −74 −78 −69 ...
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... DRVDD Full 0 Full −60 Full 50 Full 0 25°C 4 Full 247 454 Full 1.125 1.375 Twos complement, Gray code, or offset binary (default) Rev Page AD9434 AD9434-500 Min Typ Max CMOS/LVDS/LVPECL 0.9 0.2 1.8 −1.8 −0.2 −10 +10 −10 + 0.8 × DRVDD 0.2 × DRVDD 0 − ...
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... Full 50 Full 1.1 11 Full 1.1 11 Full 0.85 25°C 0.15 25°C 0.15 Full 0.6 Full 0.15 0.38 Full 15 Full 0.6 25°C 0.15 25°C 0.15 Full 0.6 Full −0.07 +0.07 Full 15 25°C 0.85 25°C 80 Rev Page AD9434-500 Min Typ Max Unit 500 MSPS 50 MSPS 0 0 0.85 ns 0.15 ns 0.15 ns 0.6 ns 0.15 0. Cycles 0.6 ns 0.15 ns 0.15 ns 0.6 ns −0.07 +0. Cycles 0 ...
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... Rev Page – – – – – – – – 11 D11 D5 D11 D5 D11 N – – – – – 11 AD9434 – – 10 ...
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... AD9434 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating Electrical AVDD to AGND −0 +2.0 V DRVDD to DRGND −0 +2.0 V AGND to DRGND −0 +0.3 V AVDD to DRVDD −2 +2.0 V D0+/D0− Through D11+/D11− −0 DRVDD + 0 DRGND DCO+, DCO− to DRGND −0 DRVDD + 0.2 V OR+, OR− ...
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... Data Clock Output—True. D0 Complement Output (LSB). D0 True Output (LSB). D1 Complement Output. D1 True Output. D2 Complement Output. D2 True Output. D3 Complement Output. D3 True Output. D4 Complement Output. Rev Page AVDD 41 AVDD 40 CML 39 AVDD 38 AVDD 37 AVDD 36 VIN– 35 VIN+ 34 AVDD 33 AVDD 32 AVDD 31 VREF 30 AVDD 29 PWDN AD9434 ...
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... AD9434 Pin No. Mnemonic 4 D4+ 5 D5− 6 D5+ 9 D6− 10 D6+ 11 D7− 12 D7+ 13 D8− 14 D8+ 15 D9− 16 D9+ 17 D10− 18 D10+ 19 D11− 20 D11+ 21 OR− 22 OR+ 1 AGND and DRGND should be tied to a common quiet ground plane. Description D4 True Output. ...
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... D1/D7 Complement Output. D1/D7 True Output. D2/D8 Complement Output. D2/D8 True Output. D3/D9 Complement Output. D3/D9 True Output. D4/D10 Complement Output. D4/D10 True Output. D5/D11 Complement Output (MSB). Rev Page AVDD 41 AVDD 40 CML 39 AVDD 38 AVDD 37 AVDD 36 VIN– 35 VIN+ 34 AVDD 33 AVDD 32 AVDD 31 VREF 30 AVDD 29 PWDN AD9434 ...
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... AD9434 Pin No. Mnemonic 6 D5/D11+ 9 OR− 20, 28 DNC 21 DNC/(OR−) 22 DNC/(OR+) 1 Tie AGND and DRGND to a common quiet ground plane. Description D5/D11 True Output (MSB). Overrange Complement Output. (This pin is disabled if Pin 21 is reconfigured through the SPI to be OR−.) Overrange True Output ...
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... Figure 9. AD9434-500 64k Point Single-Tone FFT; 500 MSPS, 30.3 MHz 120 140 160 180 Figure 10. AD9434-500 64k Point Single-Tone FFT; 500 MSPS, 100.3 MHz 120 140 160 180 Figure 11. AD9434-500 64k Point Single-Tone FFT; 500 MSPS, 140.3 MHz Rev Page ...
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... ANALOG INPUT FREQUECY (MHz) Figure 14. AD9434-370 Single-Tone SNR/SFDR vs. Input Frequency (f Temperature; 370 MSPS 200 220 240 Figure 15. AD9434-500 Single-Tone SNR/SFDR vs. Input Frequency (f 200 220 240 Figure 16. AD9434-370 SNR/SFDR vs. Sample Rate; 30.3 MHz, 100.3 MHz = +25° –40° +25°C 350 400 ...
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... SNR (dBFS SFDR (dBc SNR (dB –90 –80 –70 –60 –50 –40 AMPLITUDE (dB) Figure 18. AD9434-370 SNR/SFDR vs. Input Amplitude; 500 MSPS, 140.3 MHz 100 90 SFDR (dBFS SNR (dBFS SFDR (dBc SNR (dB –90 –80 –70 – ...
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... Figure 26. AD9434-370 64k Point, Two-Tone FFT; 370 MSPS, 119.5 MHz, 122.5 MHZ 1.17LSB rms –100 –120 MORE Figure 27. AD9434-500 64k Point, Two-Tone FFT; 500 MSPS, 119.2 MHz, 120 1.24LSB rms 100 MORE Figure 28. AD9434-370 Two-Tone SFDR vs. Input Amplitude; 370 MSPS, ...
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... SAMPLE RATE (MSPS) Figure 31. Current and Power vs. Sample Rate SFDR (dBc SNR (dBFS 1.9 2.0 500 Figure 32. SNR/SFDR for AD9434-370 and AD9434-500 at 370 MSPS and 800 700 600 500 400 300 200 100 0 = 30.3 MHz IN Rev Page AD9434, 370MSPS AD9434, 500MSPS ...
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... AD9434 EQUIVALENT CIRCUITS AVDD AVDD 0.9V 15kΩ 15kΩ CLK+ Figure 33. Clock Inputs AVDD CML AVDD VIN+ 500Ω AVDD 500Ω SPI CONTROLLED VIN+ Figure 34. Analog Input DC Equivalent Circuit (V DRVDD 350Ω SCLK/DFS 30kΩ Figure 35. Equivalent SCLK/DFS, PDWN Input Circuit VIN+ 1 ...
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... During power-down, the output buffers enter a high impedance state. ANALOG INPUT AND VOLTAGE REFERENCE The analog input to the AD9434 is a differential buffer. For best dynamic performance, match the source impedances driving VIN+ and VIN− such that common-mode settling errors are symmetrical ...
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... AD9434 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9434 and preserves the fast rise and fall times of the signal, which are critical to low jitter performance. ...
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... ANALOG INPUT FREQUENCY (MHz) Figure 48. Ideal SNR vs. Input Frequency and Jitter POWER DISSIPATION AND POWER-DOWN MODE As shown in Figure 31, the power dissipated by the AD9434 is proportional to its sample rate. The digital power dissipation does not vary much because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers. ...
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... AD9434 and must be captured on the rising edge of the DCO. In double data rate mode (DDR), data is clocked out of the AD9434 and must be captured on the rising and falling edges of the DCO. See the timing diagrams shown in Figure 2 and Figure 3 for more information ...
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... The AD9434 can be used to replace the AD9230 in many applications. In these designs, the user should consider these important differences: • Pin DNC (do not connect) on the AD9434, and should be left floating. The reset functionality of the AD9230 is not available through an external pin, but is available through the SPI interface. • ...
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... AD9434 CSB SCLK DON’T CARE W1 W0 SDIO DON’T CARE R/W Table 11. Serial Timing Definitions Parameter Min (ns CLK HIGH t 16 LOW t 1 EN_SDIO t 5 DIS_SDIO Table 12. Output Data Format Input (V) Condition (V) VIN+ − ...
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... Internal power-down mode: 0x00 000 = normal (power-up, default) 001 = full power-down 010 = standby 011 = normal (power-up) Note that external PDWN pin overrides this setting AD9434 Default Notes/ Comments The nibbles should be mirrored by the user so that LSB or MSB first mode registers correctly, regardless of shift mode ...
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... AD9434 Addr. Bit 7 (Hex) Register Name (MSB) 10 Offset 0D TEST_IO (For user-defined mode only, set Bits[3:0] = 1000 Pattern 1 only 01 = toggle P1/ toggle P1/0000 11 = toggle P1/P2/ 0000 0F AIN_CONFIG 0 14 OUTPUT_MODE 0 15 OUTPUT_ADJUST 0 16 OUTPUT_PHASE Output clock polarity 1 = inverted 0 = normal (default) 17 FLEX_OUTPUT_DELAY 0 Bit 6 Bit 5 Bit 4 Bit 3 ...
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... OR± OR± 0x01 position enable: (DDR mode (default) only off 0 = Pin 9, Pin Pin 21, Pin 0x00 coupling enable AD9434 Default Notes/ Comments User-defined pattern, 1 LSB. User-defined pattern, 1 MSB. User-defined pattern, 2 LSBs. User-defined pattern, 2 MSBs. Default is ac coupling. ...
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... Lead Frame Chip Scale Package [LFCSP_VQ] 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] LVDS Evaluation Board with AD9434BCPZ-370 LVDS Evaluation Board with AD9434BCPZ-500 D09383-0-5/11(A) Rev Page ...