AD7656-1 Analog Devices, AD7656-1 Datasheet - Page 22

• Manufacturer Part Number: AD7656-1
• Description: 250 kSPS, 6-Channel, Simultaneous Sampling, Bipolar 16-Bit ADC
• Manufacturer: Analog Devices

Specifications of AD7656-1

• Resolution (bits): 16bit
• # Chan: 6
• Sample Rate: 250kSPS
• Interface: Par,Ser,SPI
• Analog Input Type: SE-Bip
• Ain Range: 10V p-p,20 V p-p,Bip 10V,Bip 5.0V
• Adc Architecture: SAR
• Pkg Type: QFP

AD7656-1/AD7657-1/AD7658-1
The V
processor. The voltage on V
the output logic signals.
Decouple the V
decoupling capacitor. These supplies are used for the high voltage
analog input structures on the AD7656-1/AD7657-1/AD7658-1
analog inputs.
DRIVING THE ANALOG INPUTS
Together, the driver amplifier and the analog input circuit used
for the AD7656-1 must settle for a full-scale step input to a 16-bit
level (0.0015%), which is within the specified 550 ns acquisition
time of the AD7656-1. The noise generated by the driver
amplifier needs to be kept as low as possible to preserve the
SNR and transition noise performance of the AD7656-1. In
addition, the driver also needs to have a THD performance
suitable for the AD7656-1.
The
external compensation capacitor of 10 pF. If a dual version of
the AD8021 is required, the
and the
AD7658-1.
INTERFACE OPTIONS
The AD7656-1/AD7657-1/AD7658-1 provide two interface
options: a high speed parallel interface and a high speed serial
interface. The required interface mode is selected via the
SER/ PAR SEL pin. The parallel interface can operate in word
( W /B = 0) or byte ( W /B = 1) mode. When in serial mode, the
AD7656-1/AD7657-1/AD7658-1 can be configured into daisy-
chain mode.
When in parallel mode, a read operation only accesses the
results related to conversions which have just occurred. For
example, consider the case where CONVST A and CONVST C
AD8021
DRIVE
AD797
supply is connected to the same supply as the
meets these requirements. The AD8021 needs an
DD
can also be used to drive the AD7656-1/AD7657-1/
and V
SS
+9.5V TO +16.5V
–9.5V TO –16.5V
signals with a minimum 1 μF
DRIVE
AD8022
SUPPLY
2.5V
REF
SUPPLY
controls the voltage value of
ANALOG SUPPLY
VOLTAGE 5V
can be used. The
SIX ANALOG
1µF
1µF
1µF
1µF
INPUTS
+
+
+
+
1µF
+
Figure 28. Typical Connection Diagram
V
AGND
REFCAPA, B, C
AGND
REFIN/OUT
AGND
V
AGND
AD8610
DD
SS
AGND
Rev. C | Page 22 of 32
AV
CC
DV
AD7656-1/
AD7657-1/
AD7658-1
CC
DGND
are toggled simultaneously but CONVST B is not used. At
end of the conversion process when BUSY goes low a read is
implemented. Four read pulses (in parallel mode) are applied
and data from V1, V2, V5, and V6 are output. Data from V3
and V4 is not output since CONVST B was not toggled in this
cycle. However, when in serial mode all zeros are output in
place of the ADC result for ADCs not included in the conversion
cycle. See the Serial Interface section for more information.
Parallel Interface (SER/ PAR SEL = 0)
The AD7656-1/AD7657-1/AD7658-1 consist of six 16-/14-/
12-bit ADCs, respectively. A simultaneous sample of all six
ADCs can be performed by connecting all three CONVST
pins (CONVST A, CONVST B, and CONVST C) together. The
AD7656-1/AD7657-1/AD7658-1 need to see a CONVST pulse
to initiate a conversion; this should consist of a falling CONVST
edge followed by a rising CONVST edge. The rising edge of
CONVST initiates simultaneous conversions on the selected
ADCs. The AD7656-1/AD7657-1/AD7658-1 each contain an
on-chip oscillator that is used to perform the conversions. The
conversion time, t
indicate the end of a conversion. The falling edge of the BUSY
signal is used to place the track-and-hold amplifier into track mode.
The AD7656-1/AD7657-1/AD7658-1 also allow the six ADCs
to be converted simultaneously in pairs by pulsing the three
CONVST pins independently. CONVST A is used to initiate
simultaneous conversions on V1 and V2, CONVST B is used to
initiate simultaneous conversions on V3 and V4, and CONVST C
is used to initiate simultaneous conversions on V5 and V6. The
conversion results from the simultaneously sampled ADCs are
stored in the output data registers. Note that once a rising edge
occurs on any one CONVST pin to initiate a conversion, then any
further CONVST rising edges on any of the CONVST pins are
ignored while BUSY is high.
DV
CC
+
1µF
CONVST A, B, C
V
DRIVE
D0 TO D15
SER/PAR
RANGE
RESET
DGND
BUSY
STBY
W/B
H/S
CS
RD
+
CONV
DIGITAL SUPPLY
VOLTAGE +3V OR +5V
1µF
INTERFACE
PARALLEL
, is 3 μs. The BUSY signal goes low to
V
DRIVE
µP/µC/DSP