AD9627-11 Analog Devices, AD9627-11 Datasheet - Page 12

• Manufacturer Part Number: AD9627-11
• Description: 11-Bit, 105 MSPS/150 MSPS, 1.8 V Dual Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9627-11

• Resolution (bits): 11bit
• # Chan: 2
• Sample Rate: 150MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p,1 V p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9627-11
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
ELECTRICAL
ENVIRONMENTAL
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
VIN+A/VIN+B, VIN−A/VIN−B to AGND
SCLK/DFS to DRGND
SDIO/DCS to DRGND
SMI SDO/OEB
SMI SCLK/PDWN
SMI SDFS
D0A/D0B through D10A/D10B to
FD0A/FD0B through FD3A/FD3B to
DCOA/DCOB to DRGND
Operating Temperature Range
Maximum Junction Temperature
Storage Temperature Range
AVDD, DVDD to AGND
DRVDD to DRGND
AGND to DRGND
AVDD to DRVDD
CLK+, CLK− to AGND
SYNC to AGND
VREF to AGND
SENSE to AGND
CML to AGND
RBIAS to AGND
CSB to AGND
DRGND
DRGND
(Ambient)
Under Bias
(Ambient)
Rating
−0.3 V to +2.0 V
−0.3 V to +3.9 V
−0.3 V to +0.3 V
−3.9 V to +2.0 V
−0.3 V to AVDD + 0.2 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−40°C to +85°C
150°C
−65°C to +150°C
Rev. B | Page 12 of 72
THERMAL CHARACTERISTICS
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the customer
board increases the reliability of the solder joints and maximizes
the thermal capability of the package.
Table 7. Thermal Resistance
Package Type
64-Lead LFCSP
9 mm × 9 mm
(CP-64-6)
1
2
3
4
Typical θ
plane. As shown, airflow improves heat dissipation, which
reduces θ
package leads from metal traces, through holes, ground, and
power planes, reduces the θ
ESD CAUTION
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
Per MIL-Std 883, Method 1012.1.
Per JEDEC JESD51-8 (still air).
Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.
JA
JA
. In addition, metal in direct contact with the
is specified for a 4-layer PCB with a solid ground
Airflow
Velocity
(m/s)
0
1.0
2.0
JA
.
θ
18.8
16.5
15.8
JA
1, 2
θ
0.6
JC
1, 3
θ
6.0
JB
1, 4
Unit
°C/W
°C/W
°C/W