AD9627-11 Analog Devices, AD9627-11 Datasheet - Page 41

• Manufacturer Part Number: AD9627-11
• Description: 11-Bit, 105 MSPS/150 MSPS, 1.8 V Dual Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9627-11

• Resolution (bits): 11bit
• # Chan: 2
• Sample Rate: 150MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p,1 V p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 22 are not currently supported for this device.
Table 22. Memory Map Registers
Addr
(Hex)
Chip Configuration Registers
0x00
0x01
0x02
Channel Index and Transfer Registers
0x05
0xFF
ADC Functions
0x08
0x09
0x0B
0x0D
Register
Name
SPI Port
Configuration
(Global)
Chip ID
(Global)
Chip Grade
(Global)
Channel
Index
Transfer
Power Modes
Global Clock
(Global)
Clock Divide
(Global)
Test Mode
(Local)
Bit 7
(MSB)
0
Open
Open
Open
Open
Open
Open
Open
Bit 6
LSB first
Open
Open
Open
Open
Open
Open
Open
Bit 5
Soft reset
Open
Open
External
power-
down pin
function
(global)
0 = pdwn
1 = stndby
Open
Open
Reset PN23
gen
Speed grade ID
00 = 150 MSPS
10 = 105 MSPS
Bit 4
1
Open
Open
Open
Open
Open
Reset
PN9 gen
(AD9627-11 = 0x20)
Rev. B | Page 41 of 72
8-bit Chip ID[7:0]
(default)
Bit 3
1
Open
Open
Open
Open
Open
Open
Open
Bit 2
Soft reset
Open
Open
Open
Open
Open
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
Output test mode
000 = off (default)
001 = midscale short
010 = positive FS
011 = negative FS
100 = alternating checkerboard
101 = PN 23 sequence
110 = PN 9 sequence
111 = one/zero word toggle
Bit 1
LSB first
Open
Data
Channel B
(default)
Open
Internal power-down mode
(local)
00 = normal operation
01 = full power-down
10 = standby
11 = normal operation
Open
Bit 0
(LSB)
0
Open
Data
Channel A
(default)
Transfer
Duty cycle
stabilizer
(default)
0x18
0x00
Default
Value
(Hex)
0x20
0x03
0x00
0x01
0x00
0x00
AD9627-11
Default
Notes/
Comments
The nibbles
are mirrored
so that
LSB-first mode
or MSB-first
mode registers
correctly,
regardless of
shift mode
Read only
Speed grade
ID used to
differentiate
devices; read
only
Bits are set
to determine
which device
on the chip
receives the
next write
command;
applies to local
registers only
Synchronously
transfers data
from the
master shift
register to the
slave
Determines
various generic
modes of chip
operation
Clock divide
values other
than 000
automatically
cause the duty
cycle stabilizer
to become
active
When this
register is set,
the test data
is placed on
the output
pins in place of
normal data