AD7366 Analog Devices, AD7366 Datasheet - Page 20

• Manufacturer Part Number: AD7366
• Description: True Bipolar Input, Dual 12-Bit, 2-Channel, Simultaneous Sampling SAR ADC
• Manufacturer: Analog Devices

Specifications of AD7366

• Resolution (bits): 12bit
• # Chan: 4
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Bip,SE-Uni
• Ain Range: Bip (Vref) x 2,Bip (Vref) x 4,Bip 10V,Bip 5.0V,Uni (Vref) x 4,Uni 10V
• Adc Architecture: SAR
• Pkg Type: SOP

AD7366/AD7367
MODES OF OPERATION
The mode of operation of the AD7366/AD7367 is selected by
the logic state of the CNVST signal at the end of a conversion.
There are two possible modes of operation: normal mode and
shutdown mode. These modes of operation are designed to
provide flexible power management options, which can be
chosen to optimize the power dissipation/throughput rate
ratio for differing application requirements.
NORMAL MODE
Normal mode is intended for applications that require fast
throughput rates. In normal mode, the AD7366/AD7367
remain fully powered at all times, so the user does not need to
worry about power-up times. Figure 22 shows the general mode
of operation of the AD7366 in normal mode; Figure 23 shows
normal mode for the AD7367.
The conversion is initiated on the falling edge of CNVST as
described in the Circuit Information section. To ensure that
the part remains fully powered up at all times, CNVST must be
at logic state high before the BUSY signal goes low. If CNVST is
at logic state low when the BUSY signal goes low, the analog
circuitry powers down and the part ceases converting. The
BUSY signal remains high for the duration of the conversion.
CNVST
CNVST
BUSY
BUSY
SCLK
SCLK
CS
CS
t
t
2
2
SERIAL READ OPERATION
t
SERIAL READ OPERATION
t
1
1
t
t
CONVERT
Figure 22. Normal Mode Operation for the AD7366
CONVERT
Figure 23. Normal Mode Operation for the AD7367
Rev. D | Page 20 of 28
1
1
t
t
3
3
The CS pin must be brought low to bring the data bus out of
three-state. Therefore, 12 SCLK cycles are required to read the
conversion result from the AD7366 and 14 SCLK cycles are
required to read the conversion result from the AD7367. The
D
CS is left low for an additional 12 SCLK cycles for the AD7366 or
14 SCLK cycles for the AD7367, the result from the other on-chip
ADC is also accessed on the same D
and Figure 28 (see the Serial Interface section).
When 24 SCLK cycles have elapsed for the AD7366 or 28 SCLK
cycles for the AD7367, the D
when CS is brought high, not on the 24
edge. If CS is brought high prior to this, the D
three-state at that point. Thus, CS must be brought high when
the read is completed, because the bus does not automatically
return to three-state upon completion of the dual result read.
When a data transfer is complete and D
returned to three-state, another conversion can be initiated after
the quiet time, t
OUT
lines return to three-state only when CS is brought high. If
QUIET
t
t
QUIET
QUIET
, has elapsed by bringing CNVST low again.
12
14
OUT
line returns to three-state only
OUT
line, as shown in Figure 27
th
OUT
or 28
A and D
OUT
th
SCLK falling
line returns to
OUT
B have