AD7796 Analog Devices, AD7796 Datasheet - Page 13

• Manufacturer Part Number: AD7796
• Description: Low Power 16-Bit Sigma-Delta A/D Converter for Bridge Sensors
• Manufacturer: Analog Devices

Specifications of AD7796

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: n/a
• Interface: Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: ± (Vref/128)
• Adc Architecture: Sigma-Delta
• Pkg Type: SOP

Table 13. Operating Modes
MD2
0
0
0
0
1
1
1
1
Table 14. Update Rates Available
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
MD1
0
0
1
1
0
0
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
MD0
0
1
0
1
0
1
0
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Mode
Continuous Conversion Mode (default). In continuous conversion mode, the ADC continuously performs
conversions and places the result in the data register. RDY goes low when a conversion is complete. The user can
read these conversions by placing the device in continuous read mode, whereby the conversions are automatically
placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to output the
conversion by writing to the communication register. After a power-on, channel change, or write to the mode or
configuration register, the first conversion is available after a period of 2/f
available at a frequency of f
Single Conversion Mode. When single conversion mode is selected, the ADC powers up and performs a single
conversion. The oscillator requires 1 ms to power up and settle. The ADC then performs the conversion, which takes
a time of 2/f
down mode. The conversion remains in the data register and RDY remains active (low) until the data is read or
another conversion is performed.
Idle Mode. In idle mode, the ADC filter and modulator are held in a reset state although the modulator clocks are
still provided.
Power-Down Mode. In power-down mode, all the AD7796/AD7797 circuitry is powered down, including the
burnout currents and CLKOUT circuitry.
Internal Zero-Scale Calibration. An internal short is automatically connected to the channel. A calibration takes
two conversion cycles to complete. RDY goes high when the calibration is initiated and returns low when the
calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is
placed in the offset register.
Reserved.
System Zero-Scale Calibration. Users should connect the system zero-scale input to the channel input pins.
A system offset calibration takes two conversion cycles to complete. RDY goes high when the calibration is
initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration.
The measured offset coefficient is placed in the offset register.
System Full-Scale Calibration. Users should connect the system full-scale input to the channel input pins.
A calibration takes two conversion cycles to complete. RDY goes high when the calibration is initiated and returns
low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-
scale coefficient is placed in the full-scale register.
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
ADC
. The conversion result is placed in the data register, RDY goes low, and the ADC returns to power-
f
X
X
X
123
62
50
X
33.2
X
16.7
16.7
12.5
10
8.33
6.25
4.17
ADC
(Hz)
ADC
.
t
X
X
X
16
32
40
X
60
X
120
120
160
200
240
320
480
SETTLE
Rev. A | Page 13 of 24
(ms)
Rejection @ 50 Hz/60 Hz (Internal Clock)
80 dB (50 Hz only)
65 dB (50 Hz and 60 Hz)
66 dB (50 Hz and 60 Hz)
69 dB (50 Hz and 60 Hz)
70 dB (50 Hz and 60 Hz)
72 dB (50 Hz and 60 Hz)
74 dB (50 Hz and 60 Hz)
ADC
, while subsequent conversions are
AD7796/AD7797