AD7686 Analog Devices, AD7686 Datasheet - Page 22

• Manufacturer Part Number: AD7686
• Manufacturer: Analog Devices

Specifications of AD7686

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 500kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p
• Adc Architecture: SAR
• Pkg Type: CSP,SOIC,SOP

AD7686
CHAIN MODE WITH BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7686s
on a 3-wire serial interface while providing a busy indicator.
This feature is useful for reducing component count and
wiring connections, for example, in isolated multiconverter
applications or for systems with a limited interfacing capacity.
Data readback is analogous to clocking a shift register. A
connection diagram example using three AD7686s is shown in
Figure 43, and the corresponding timing is given in Figure 44.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the busy indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
completed their conversions, the nearend ADC (ADC C in
Figure 43) SDO is driven high.
ACQUISITION
SDO
SDO
CNV = SDI
t
HSCKCNV
A
B
SCK
= SDI
= SDI
SDO
B
C
C
A
SDI
CONVERSION
t
t
DSDOSDI
t
SSCKCNV
t
AD7686
CONV
DSDOSDI
t
EN
CNV
SCK
A
SDO
t
t
t
SSDISCK
HSDO
DSDO
1
D
D
D
C
A
B
2
15 D
15 D
15 D
Figure 44. Chain Mode with Busy Indicator Serial Interface Timing
Figure 43. Chain Mode with Busy Indicator Connection Diagram
C
A
3
B
14 D
14 D
14 D
t
SDI
SCKH
C
t
A
B
4
HSDISCK
13
13
13
AD7686
CNV
SCK
B
15
t
SCK
Rev. B | Page 22 of 28
D
D
D
SDO
16
C
A
B
1
1
1
t
SCKL
D
D
D
17
C
A
B
0
0
0 D
D
ACQUISITION
18
B
A
15 D
15 D
t
CYC
This transition on SDO can be used as a busy indicator to
trigger the data readback controlled by the digital host. The
AD7686 then enters the acquisition phase and powers down.
The data bits stored in the internal shift register are then
clocked out, MSB first, by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 16 × N + 1 clocks are required to
readback the N ADCs.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate and, consequently, more AD7686s in the chain, provided
the digital host has an acceptable hold time. For instance,
with a 3 ns digital host setup time and 3 V interface, up to four
AD7686s running at a conversion rate of 360 kSPS can be daisy
chained to a single 3-wire port.
19
B
SDI
A
t
14
14
ACQ
AD7686
CNV
SCK
31
C
D
D
32
B
A
SDO
1
1
D
D
33
B
A
0 D
0
34
A
15
D
35
A
14
CONVERT
DATA IN
IRQ
CLK
DIGITAL HOST
47
t
DSDOSDI
D
48
t
DSDOSDI
A
t
1
DSDOSDI
D
49
A
0