AD7685 Analog Devices, AD7685 Datasheet
AD7685
Specifications of AD7685
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AD7685 Summary of contents
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... V, 2 logic using the 49152 65536 separate supply VIO. The AD7685 is housed in a 10-lead MSOP or a 10-lead QFN (LFCSP) with operation specified from −40°C to +85°C. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ...
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... Chain Mode, No BUSY Indicator ............................................ 22 Chain Mode with BUSY Indicator........................................... 23 Application Hints ........................................................................... 24 Layout .......................................................................................... 24 Evaluating the Performance of the AD7685............................... 24 True 16-Bit Isolated Application Example .............................. 25 Outline Dimensions ....................................................................... 26 Ordering Guide .......................................................................... 27 12/04—Rev Rev. A Changes to Specifications.................................................................3 Changes to Figure 17 Captions..................................................... 11 Changes to Power Supply Section ...
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... Rev Page AD7685 B Grade C Grade Typ Max Min Typ Max REF REF VDD + −0.1 VDD + 0.1 0.1 +0.1 −0.1 +0 See the See the ...
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... AD7685 VDD = 2 5.5 V, VIO = 2 VDD, V Table 3. Parameter Conditions REFERENCE Voltage Range Load Current 250 kSPS, REF = 5 V SAMPLING DYNAMICS −3 dB Input Bandwidth Aperture Delay VDD = 5 V DIGITAL INPUTS Logic Levels DIGITAL OUTPUTS Data Format Pipeline Delay ...
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... ACQ t CYC t CNVH t SCK t SCK t SCKL t SCKH t HSDO t DSDO DIS t SSDICNV t HSDICNV t SSCKCNV t HSCKCNV t SSDISCK t HSDISCK t DSDOSDI Rev Page AD7685 Min Typ Max Unit 0.5 2.2 μs 1.8 μs 4 μ ...
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... AD7685 −40°C to +85°C, VIO = 2 4 VDD + 0.3 V, whichever is the lowest, unless otherwise stated. 1 Table 5. VDD = 2.3V to 4.5 V Parameter Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time Between Conversions CNV Pulse Width (CS Mode) SCK Period (CS Mode) SCK Period (Chain Mode) VIO Above 3 V VIO Above 2 ...
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... This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev Page AD7685 ...
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... AI = analog input digital input digital output, and P = power. VIO SDI SCK SDO CNV Rev Page REF 1 10 VIO VDD 2 9 SDI AD7685 IN SCK TOP VIEW (Not to Scale) IN– SDO GND 5 6 CNV NOTES 1. EXPOSED PAD CONNECTED TO GND. THIS CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES ...
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... Aperture delay is a measure of the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion. Transient Response The time required for the ADC to accurately acquire its input after a full-scale step function is applied. Rev Page AD7685 ...
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... AD7685 TYPICAL PERFORMANCE CHARACTERISTICS 2.0 POSITIVE INL = +0.33LSB NEGATIVE INL = –0.50LSB 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0 16384 32768 CODE Figure 7. Integral Nonlinearity vs. Code 250000 204292 200000 150000 100000 50000 29041 27755 80E5 80E6 80E7 80E8 80E9 80EA 80EB 80EC 80ED CODE IN HEX Figure 8 ...
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... Rev Page THD SFDR 2.7 3.1 3.5 3.9 4.3 4.7 5.1 REFERENCE VOLTAGE (V) Figure 16. THD, SFDR vs. Reference Voltage V = 5V, –1dB REF V = 2.5V, –1dB REF V = 5V, –10dB REF 50 100 150 FREQUENCY (kHz) Figure 17. THD vs. Frequency V = 2.5V REF REF –35 – 105 TEMPERATURE (°C) Figure 18. THD vs. Temperature AD7685 5.5 200 125 ...
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... AD7685 95 94 SNR 93 92 THD 91 90 –10 –8 –6 –4 INPUT LEVEL (dB) Figure 19. SNR and THD vs. Input Level 1000 750 VDD 500 250 VIO 0 2.3 2.7 3.1 3.5 3.9 4.3 SUPPLY (V) Figure 20. Operating Currents vs. Supply 1000 750 500 250 VDD + VIO 0 –55 –35 – TEMPERATURE (°C) Figure 21. Power-Down Currents vs. Temperature – ...
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... The AD7685 is specified from 2 5.5 V and can be interfaced to any 1 digital logic family housed in a 10-lead MSOP or a tiny 10-lead QFN (LFCSP) that combines space savings and allows flexible configurations ...
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... AD7685 Transfer Functions The ideal transfer characteristic for the AD7685 is shown in Figure 26 and Table 8. 111...111 111...110 111...101 000...010 000...001 000...000 –FS – LSB –FS + 0.5 LSB ANALOG INPUT Figure 26. ADC Ideal Transfer Function ≥7V ≥ VREF 3 ≤ ...
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... When the source impedance of the driving circuit is low, the AD7685 can be driven directly. Large source impedances significantly affect the ac performance, especially THD. The dc performances are less sensitive to the input impedance. The ...
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... The noise coming from the amplifier is filtered by the AD7685 analog input circuit low- pass filter made by R and external filter, if one used. Because the typical noise of the AD7685 is 35 μV rms, the SNR degradation due to the amplifier is ⎛ ⎜ ⎜ ...
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... SDI hold time is such that when SDI and CNV are connected together, the chain mode is always selected. In either the CS mode or the chain mode, the AD7685 offers the flexibility to optionally force a start bit in front of the data bits. This start bit can be used as a BUSY signal indicator to interrupt the digital host and trigger the data reading ...
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... AD7685 CS MODE 3-WIRE, NO BUSY INDICATOR This mode is usually used when a single AD7685 is connected to an SPI-compatible digital host. The connection diagram is shown in Figure 34, and the corresponding timing is given in Figure 35. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance ...
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... CS MODE 3-WIRE WITH BUSY INDICATOR This mode is usually used when a single AD7685 is connected to an SPI-compatible digital host having an interrupt input. The connection diagram is shown in Figure 36, and the corresponding timing is given in Figure 37. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance ...
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... SCK falling edge, or when SDI goes high, whichever is earlier, SDO returns to high impedance and another AD7685 can be read. If multiple AD7685s are selected at the same time, the SDO output pin handles this contention without damage or induced latch-up. Meanwhile recommended to keep this contention as short as possible to limit extra power dissipation ...
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... CS MODE 4-WIRE WITH BUSY INDICATOR This mode is usually used when a single AD7685 is connected to an SPI-compatible digital host, which has an interrupt input, and it is desired to keep CNV, which is used to sample the analog input, independent of the signal used to select the data reading. This requirement is particularly important in applications where low jitter on CNV is desired ...
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... AD7685s in the chain, provided the digital host has an acceptable hold time. The maximum conversion rate may be reduced due to the total readback time. For instance, with digital host setup time and 3 V interface eight AD7685s running at a conversion rate of 220 kSPS can be daisy-chained on a 3-wire port. ...
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... CHAIN MODE WITH BUSY INDICATOR This mode can also be used to daisy chain multiple AD7685s on a 3-wire serial interface while providing a BUSY indicator. This feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register ...
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... The pinout of the AD7685 with all its analog signals on the left side and all its digital signals on the right side eases this task. Avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the AD7685 is used as a shield ...
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... Figure 48. A True 16-Bit Isolated Simultaneous Sampling Acquisition System Multiple AD7685s are daisy-chained to reduce the number of signals to isolate. Note that the SCKOUT, which is a readback of the AD7685’s clock, has a very short skew with the DATA signal. This skew is the channel-to-channel matching propagation delay of the digital isolator (t ...
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... AD7685 OUTLINE DIMENSIONS IDENTIFIER PIN 1 INDEX AREA 0.80 0.75 0.70 SEATING PLANE 3.10 3.00 2.90 5. 3.10 4.90 3.00 4.65 1 2.90 5 PIN 1 0.50 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.15 0.23 6° 0.30 0.05 0.13 0° 0.15 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 49.10-Lead Micro Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 3.10 3.00 SQ 2.90 6 0.50 0.40 0.30 5 TOP VIEW BOTTOM VIEW 0.05 MAX 0.02 NOM 0.30 0.20 REF ...
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... AD7685ARMZRL7 ±6 LSB max AD7685BCPZRL ±3 LSB max AD7685BCPZRL7 ±3 LSB max AD7685BRMZ ±3 LSB max AD7685BRMZRL7 ±3 LSB max AD7685CCPZRL ±2 LSB max AD7685CCPZRL7 ±2 LSB max AD7685CRMZ ±2 LSB max AD7685CRMZRL7 ±2 LSB max 2 EVAL-AD7685CBZ 3 EVAL-CONTROL BRD2Z 3 EVAL-CONTROL BRD3Z RoHS Compliant Part ...
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... AD7685 NOTES ©2004–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02968-0-8/11(C) Rev Page ...