AD7666 Analog Devices, AD7666 Datasheet
AD7666
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AD7666 Summary of contents
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... The AD7666 is available in a 48-lead LQFP and a tiny 48-lead LFCSP, with operation specified from –40°C to +85°C. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. ...
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... Conversion Control.................................................................... 21 REVISION HISTORY Revision 0: Initial Version Digital Interface.......................................................................... 22 Parallel Interface......................................................................... 22 Serial Interface ............................................................................ 22 Master Serial Interface............................................................... 23 Slave Serial Interface .................................................................. 24 Microprocessor Interfacing....................................................... 26 Application Hints ........................................................................... 27 Bipolar and Wider Input Ranges .............................................. 27 Layout .......................................................................................... 27 Evaluating the AD7666’s Performance .................................... 27 Outline Dimensions ....................................................................... 28 Ordering Guide .......................................................................... 28 Rev Page ...
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... Input kHz IN Full-Scale Step V @ 25°C 2.493 REF –40°C to +85°C –40°C to +85°C AVDD = 5 V ± µF REF 2.3 500 kSPS Throughput Rev Page AD7666 Typ Max Unit Bits V V REF + 7.7 µA 2 µs ...
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... AD7666 Parameter DIGITAL INPUTS Logic Levels DIGITAL OUTPUTS 5 Data Format Pipeline Delay POWER SUPPLIES Specified Performance AVDD DVDD OVDD Operating Current 8 AVDD 9 AVDD 10 DVDD 10 OVDD 8, 10 Power Dissipation without REF Power Dissipation with REF 8, 10 ...
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... L Rev Page AD7666 Min Typ Max 1. 1.25 750 10 1. 525 ...
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... AD7666 Table 4. Serial Clock Timings in Master Read after Convert DIVSCLK[1] DIVSCLK[0] SYNC to SCLK First Edge Delay Minimum Internal SCLK Period Minimum Internal SCLK Period Maximum Internal SCLK HIGH Minimum Internal SCLK LOW Minimum SDOUT Valid Setup Time Minimum SDOUT Valid Hold Time Minimum ...
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... ABSOLUTE MAXIMUM RATINGS 1 Table 5. AD7666 Stress Ratings Parameter Rating TEMP , REF, REFBUFIN, INGND, AVDD + 0 REFGND to AGND Ground Voltage Differences AGND, DGND, OGND ±0.3 V Supply Voltages AVDD, DVDD, OVDD –0 AVDD to DVDD, AVDD to OVDD ±7 V DVDD to OVDD –0 Digital Inputs – ...
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... When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal active in both master and slave modes AGND PIN 1 AVDD IDENTIFIER BYTESWAP 4 OB/2C 5 AD7666 NC 6 TOP VIEW NC 7 (Not to Scale) SER/PAR D2/DIVSCLK0 11 D3/DIVSCLK1 ...
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... Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled also used to gate the external clock. 33 RESET DI Reset Input. When set to a logic HIGH, this pin resets the AD7666 and the current conversion, if any, is aborted. If not used, this pin could be tied to DGND Power-Down Input ...
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... AD7666 1 Pin No. Mnemonic Type Description Primary Analog Input with a Range 2 TEMP AO Temperature Sensor Voltage Output. 46 REFBUFIN AI/O Reference Input Voltage. The reference output and the reference buffer input. 47 PDREF DI This pin allows the choice of internal or external voltage references. When LOW, the on-chip reference is turned on ...
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... Aperture delay is a measure of the acquisition performance and is measured from the falling edge of the CNVST input to when the input signal is held for a conversion. Transient Response Transient response is the time required for the AD7666 to achieve its rated accuracy after a full-scale step function is applied to its input. Reference Voltage Temperature Coefficient ...
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... AD7666 TYPICAL PERFORMANCE CHARACTERISTICS 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0 16384 32768 CODE Figure 5. Integral Nonlinearity vs. Code 0.5 1.0 POSITIVE INL (LSB) Figure 6. Typical Positive INL Distribution (99 Units 0.25 0.50 0.75 1.00 POSITIVE DNL (LSB) Figure 7. Typical Positive DNL Distribution (99 Units) 1.5 1.0 0.5 0 –0.5 –1.0 49152 ...
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... Figure 14. Histogram of 261,120 Conversions Input at the Code Center SFDR SECOND THD HARMONIC THIRD HARMONIC 1 10 100 FREQUENCY (kHz) Figure 15. THD, Harmonics, and SFDR vs. Frequency SNR S/[N+D] –50 –40 –30 –20 –10 INPUT LEVEL (dB) AD7666 34 0 8002 120 110 100 1000 0 ...
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... AD7666 92 91 ENOB –55 –35 – TEMPERATURE (°C) Figure 17. SNR, S/(N+D), and ENOB vs. Temperature –100 –105 THD –110 SECOND HARMONIC –115 –55 –35 – TEMPERATURE (°C) Figure 18. THD and Harmonics vs. Temperature 100000 10000 1000 100 AVDD ...
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... OVDD = 2.7V @ 85°C 45 OVDD = 2.7V @ 25° OVDD = 5V @ 85°C 20 OVDD = 5V @ 25° 100 150 C (pF) L Figure 23. Typical Delay vs. Load Capacitance, C 200 L Rev Page AD7666 ...
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... ADC that does not exhibit any pipeline or latency, making it ideal for multiple multiplexed channel applications. The AD7666 can be operated from a single 5 V supply and can be interfaced to either digital logic housed in either a 48-lead LQFP or a 48-lead LFCSP that saves space and allows flexible configurations as either a serial or parallel inter- face ...
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... Transfer Functions Using the OB/ 2C digital input, the AD7666 offers two output codings: straight binary and twos complement. The LSB size is V /65536, which is about 38.15 µV. The AD7666’s ideal REF transfer characteristic is shown in Figure 25 and Table 7. 1 LSB = V /65536 REF 111 ...
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... Figure 29. THD vs. Analog Input Frequency and Source Resistance Driver Amplifier Choice Although the AD7666 is easy to drive, the driver amplifier needs to meet the following requirements: • The driver amplifier and the AD7666 analog input circuit must be able to settle for a full-scale step of the capacitor array at a 16-bit level (0.0015%). In the amplifier’ ...
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... Voltage Reference Input The AD7666 allows the choice of either a very low temperature drift internal voltage reference or an external 2.5 V reference. Unlike many ADCs with internal references, the internal reference of the AD7666 provides excellent performance and can be used in almost all applications ...
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... AD780 can be selected with reference voltage. The TEMP pin, which measures the temperature of the AD7666, can be used as shown in Figure 30. The output of TEMP pin is applied to one of the inputs of the analog switch (e.g., ADG779), and the ADC itself is used to measure its own temperature. This configuration is very useful for improving the calibration accuracy over the temperature range ...
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... PD, until the conversion is complete. CNVST operates independently of CS and RD . Conversions can be automatically initiated with the AD7666. If CNVST is held LOW when BUSY is LOW, the AD7666 controls the acquisition phase and automatically initiates a new conversion. By keeping CNVST LOW, the AD7666 keeps the conversion process running by itself ...
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... D[15:8] or D[7:0]. SERIAL INTERFACE The AD7666 is configured to use the serial interface when SER/ PAR is held HIGH. The AD7666 outputs 16 bits of data, MSB first, on the SDOUT pin. This data is synchronized with the 16 clock pulses provided on the SCLK pin. The output data is valid on both the rising and falling edges of the data clock ...
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... Figure 40. Master Serial Data Timing for Reading (Read Previous Conversion during Convert) Usually, because the AD7666 is used with a fast throughput, the Master Read During Conversion mode is the most recommen- ded serial mode. In this mode, the serial clock and data toggle at appropriate instants, minimizing potential feedthrough between digital activity and critical conversion decisions ...
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... Figure 42. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert) While the AD7666 is performing a bit decision important that voltage transients be avoided on digital input/output pins or degradation of the conversion result could occur. This is particularly important during the second half of the conversion ...
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... MHz, which accommodates both the slow digital host interface and the fastest serial reading. Finally, in this mode only, the AD7666 provides a daisy-chain feature using the RDC/SDIN pin for cascading multiple con- verters together. This feature is useful for reducing component count and wiring connections when desired, as, for instance, in isolated multiconverter applications ...
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... Figure 44 shows an interface diagram between the AD7666 and the SPI equipped ADSP-219x. To accommodate the slower speed of the DSP, the AD7666 acts as a slave device and data must be read after conversion. This mode also allows the daisy- chain feature. The convert command can be initiated in response to an internal timer interrupt ...
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... ADC to further reduce low frequency ripple. INGND The DVDD supply of the AD7666 can be a separate supply, or REF can come from the analog supply AVDD or the digital interface supply OVDD. When the system digital supply is noisy or when ...
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... SEATING PLANE ORDERING GUIDE Model AD7666AST AD7666ASTRL AD7666ACP AD7666ACPRL 1 EVAL-AD7666CB 2 EVAL-CONTROL BRD2 1 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes. 2 This board allows control and communicate with all Analog Devices evaluation boards ending in the CB designators. ...