AD7667 Analog Devices, AD7667 Datasheet

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AD7667

Manufacturer Part Number
AD7667
Description
Manufacturer
Analog Devices
Datasheet

Specifications of AD7667

Resolution (bits)
16bit
# Chan
1
Sample Rate
1MSPS
Interface
Par,Ser,SPI
Analog Input Type
Diff-Uni
Ain Range
(Vref) p-p,2.5V p-p,Uni (Vref),Uni 2.5V
Adc Architecture
SAR
Pkg Type
CSP,QFP

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Quantity:
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FEATURES
2.5 V internal reference: typical drift 3 ppm/°C
Throughput:
INL: ±2.0 LSB max (±0.0038% of full scale)
16-bit resolution with no missing codes
S/(N+D): 88 dB min @ 20 kHz
THD: –96 dB max @ 20 kHz
Analog input voltage range: 0 V to 2.5 V
No pipeline delay
Parallel and serial 5 V/3 V interface
SPI
Single 5 V supply operation
Power dissipation
48-lead LQFP and 48-lead LFCSP packages
Pin-to-pin compatible with AD7671, AD7677
APPLICATIONS
Data acquisition
Medical instruments
Digital signal processing
Battery-powered systems
Process control
GENERAL DESCRIPTION
The AD7667 is a 16-bit, 1 MSPS, charge redistribution SAR
analog-to-digital converter that operates from a single 5 V
power supply. The part contains a high speed 16-bit sampling
ADC, an internal conversion clock, internal reference, error
correction circuits, and both serial and parallel system inter-
face ports. It features a very high sampling rate mode (Warp), a
fast mode (Normal) for asynchronous applications, and a
reduced power mode (Impulse) for low power applications
where power is scaled with the throughput. The AD7667 is
hardware factory-calibrated and comprehensively tested to
ensure ac parameters such as signal-to-noise ratio (SNR) and
total harmonic distortion (THD) in addition to the more
traditional dc parameters of gain, offset, and linearity. Operation
is specified from –40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Guaranteed max drift 15 ppm/°C
1 MSPS (Warp mode)
800 kSPS (Normal mode)
666 kSPS (Impulse mode)
87 mW typ @ 666 kSPS, 130 µW @ 1 kSPS without REF
133 mW typ @1 MSPS with REF
®
/QSPI
TM
/MICROWIRE
TM
/DSP compatible
PDREF
PDBUF
RESET
Table 1. PulSAR Selection
Type/kSPS
Pseudo-
Differential
True Bipolar
True
Differential
18-Bit
Multichannel/
Simultaneous
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
INGND
AGND
AVDD
PD
IN
Unipolar ADC with Reference
Fast Throughput.
The AD7667 is a 1 MSPS, charge redistribution, 16-bit SAR
ADC with internal error correction circuitry.
Superior INL.
The AD7667 has a maximum integral nonlinearity of
2.0 LSBs with no missing 16-bit codes.
Internal Reference.
The AD7667 has an internal reference with a typical
temperature drift of 3 ppm/°C.
Single-Supply Operation.
The AD7667 operates from a single 5 V supply. In Impulse
mode, its power dissipation decreases with throughput.
Serial or Parallel Interface.
Versatile parallel or 2-wire serial interface arrangement is
compatible with both 3 V and 5 V logic.
WARP
REFBUFIN
REF
CALIBRATION CIRCUITRY
FUNCTIONAL BLOCK DIAGRAM
CONTROL LOGIC AND
IMPULSE
16-Bit 1 MSPS PulSAR
100–250
AD7651
AD7660/AD7661
AD7663
AD7675
AD7678
SWITCHED
CAP DAC
REF REFGND
© 2004 Analog Devices, Inc. All rights reserved.
CNVST
CLOCK
AD7667
Figure 1.
500–570
AD7650/AD7652
AD7664/AD7666
AD7665
AD7676
AD7679
AD7654
AD7655
INTERFACE
PARALLEL
DVDD
SERIAL
PORT
DGND
www.analog.com
16
AD7667
OVDD
OGND
DATA[15:0]
BUSY
RD
CS
SER/PAR
OB/2C
BYTESWAP
800–
1000
AD7653
AD7667
AD7671
AD7677
AD7674
®

Related parts for AD7667

AD7667 Summary of contents

Page 1

... Internal Reference. The AD7667 has an internal reference with a typical temperature drift of 3 ppm/°C. 4. Single-Supply Operation. The AD7667 operates from a single 5 V supply. In Impulse mode, its power dissipation decreases with throughput. 5. Serial or Parallel Interface. Versatile parallel or 2-wire serial interface arrangement is compatible with both 3 V and 5 V logic. ...

Page 2

... Conversion Control.................................................................... 21 REVISION HISTORY Revision 0: Initial Version. Digital Interface.......................................................................... 22 Parallel Interface......................................................................... 22 Serial Interface ............................................................................ 22 Master Serial Interface............................................................... 23 Slave Serial Interface .................................................................. 24 Microprocessor Interfacing....................................................... 26 Application Hints ........................................................................... 27 Bipolar and Wider Input Ranges .............................................. 27 Layout .......................................................................................... 27 Evaluating the AD7667’s Performance .................................... 27 Outline Dimensions ....................................................................... 28 Ordering Guide .......................................................................... 28 Rev Page ...

Page 3

... Input kHz IN Full-Scale Step V @ 25°C 2.493 REF –40°C to +85°C –40°C to +85°C AVDD = 5 V ± µF REF 2.3 1 MSPS Throughput Rev Page AD7667 Typ Max Unit Bits V V REF + µA 1 µs ...

Page 4

... AD7667 Parameter DIGITAL INPUTS Logic Levels DIGITAL OUTPUTS 5 Data Format Pipeline Delay POWER SUPPLIES Specified Performance AVDD DVDD OVDD 8 Operating Current 9 AVDD 10 AVDD 11 DVDD 11 OVDD 9, 11 Power Dissipation without REF Power Dissipation with REF ...

Page 5

... L Rev Page AD7667 Min Typ Max 10 1/1.25/1.5 35 0.75/1/1. 0.75/1/1.25 250 10 0.75/1/1. 25/275/525 ...

Page 6

... AD7667 Table 4. Serial Clock Timings in Master Read after Convert DIVSCLK[1] DIVSCLK[0] SYNC to SCLK First Edge Delay Minimum Internal SCLK Period Minimum Internal SCLK Period Maximum Internal SCLK HIGH Minimum Internal SCLK LOW Minimum SDOUT Valid Setup Time Minimum SDOUT Valid Hold Time Minimum ...

Page 7

... ABSOLUTE MAXIMUM RATINGS 1 Table 5. AD7667 Stress Ratings Parameter Rating TEMP , REF, REFBUFIN, AVDD + 0 INGND, REFGND to AGND Ground Voltage Differences AGND, DGND, OGND ±0.3 V Supply Voltages AVDD, DVDD, OVDD –0 AVDD to DVDD, AVDD to OVDD ±7 V DVDD to OVDD –0 Digital Inputs – ...

Page 8

... INVSYNC DI/O INVSCLK AGND PIN 1 AVDD IDENTIFIER BYTESWAP 4 OB/2C 5 AD7667 WARP 6 TOP VIEW IMPULSE 7 (Not to Scale) SER/PAR D2/DIVSCLK0 11 D3/DIVSCLK1 CONNECT Figure 4. 48-Lead LQFP (ST-48) and 48-Lead LFCSP (CP-48) Description Analog Power Ground Pin ...

Page 9

... Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled also used to gate the external clock. Reset Input. When set to a logic HIGH, this pin resets the AD7667 and the current conversion, if any, is aborted. If not used, this pin could be tied to DGND. ...

Page 10

... AD7667 1 Pin No. Mnemonic Type 45 TEMP AO 46 REFBUFIN AI/O 47 PDREF DI 48 PDBUF Analog Input; AI/O = Bidirectional Analog Analog Output Digital Input; DI/O = Bidirectional Digital Digital Output Power. Description Temperature Sensor Voltage Output. Reference Input Voltage. The reference output and the reference buffer input. This pin allows the choice of internal or external voltage references. When LOW, the on-chip reference is turned on ...

Page 11

... Aperture delay is a measure of the acquisition performance and is measured from the falling edge of the CNVST input to when the input signal is held for a conversion. Transient Response Transient response is the time required for the AD7667 to achieve its rated accuracy after a full-scale step function is applied to its input. Reference Voltage Temperature Coefficient ...

Page 12

... AD7667 TYPICAL PERFORMANCE CHARACTERISTICS 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0 16384 32768 CODE Figure 5. Integral Nonlinearity vs. Code 0.5 1.0 POSITIVE INL (LSB) Figure 6. Typical Positive INL Distribution (102 Units 0.25 0.50 0.75 1.00 POSITIVE DNL (LSB) Figure 7. Typical Positive DNL Distribution (102 Units) 1.5 1.0 0.5 0 –0.5 – ...

Page 13

... Figure 14. Histogram of 261,120 Conversions Input at the Code Center SFDR SECOND HARMONIC THD THIRD HARMONIC 1 10 100 FREQUENCY (kHz) Figure 15. THD, Harmonics, and SFDR vs. Frequency SNR S/[N+D] –50 –40 –30 –20 –10 INPUT LEVEL (dB) AD7667 16 0 8006 120 110 100 1000 0 ...

Page 14

... AD7667 92 ENOB 91 SNR 90 S/[N+ –55 –35 – TEMPERATURE (°C) Figure 17. SNR, S/[N+D], and ENOB vs. Temperature –100 THD –105 SECOND HARMONIC –110 THIRD HARMONIC –115 –55 –35 – TEMPERATURE (°C) Figure 18. THD and Harmonics vs. Temperature 100000 AVDD, WARP/NORMAL ...

Page 15

... OVDD = 2.7V @ 85°C 45 OVDD = 2.7V @ 25° OVDD = 5V @ 85°C 20 OVDD = 5V @ 25° 100 150 C (pF) L Figure 23. Typical Delay vs. Load Capacitance C 200 L Rev Page AD7667 ...

Page 16

... ADC that does not exhibit any pipeline or latency, making it ideal for multiple multiplexed channel applications. The AD7667 can be operated from a single 5 V supply and can be interfaced to either digital logic housed in either a 48-lead LQFP or a 48-lead LFCSP that saves space and allows flexible configurations as either a serial or parallel inter- face ...

Page 17

... Transfer Functions Using the OB/ 2C digital input, the AD7667 offers two output codings: straight binary and twos complement. The LSB size is V /65536, which is about 38.15 µV. The AD7667’s ideal REF transfer characteristic is shown in Figure 25 and Table 7. 1 LSB = V /65536 REF 111 ...

Page 18

... Figure 29. THD vs. Analog Input Frequency and Source Resistance Driver Amplifier Choice Although the AD7667 is easy to drive, the driver amplifier needs to meet the following requirements: • The driver amplifier and the AD7667 analog input circuit must be able to settle for a full-scale step of the capacitor array at a 16-bit level (0.0015%). In the amplifier’ ...

Page 19

... Voltage Reference Input The AD7667 allows the choice of either a very low temperature drift internal voltage reference or an external 2.5 V reference. Unlike many ADCs with internal references, the internal reference of the AD7667 provides excellent performance and can be used in almost all applications ...

Page 20

... The AD780 can be selected with reference voltage. The TEMP pin, which measures the temperature of the AD7667, can be used as shown in Figure 30. The output of TEMP pin is applied to one of the inputs of the analog switch (e.g., ADG779), and the ADC itself is used to measure its own temperature ...

Page 21

... PD, until the conversion is complete. CNVST operates independently of CS and Impulse mode, conversions can be automatically initiated. If CNVST is held LOW when BUSY is LOW, the AD7667 controls the acquisition phase and automatically initiates a new con- version. By keeping CNVST LOW, the AD7667 keeps the conversion process running by itself ...

Page 22

... D[15:8] or D[7:0]. SERIAL INTERFACE The AD7667 is configured to use the serial interface when SER/ PAR is held HIGH. The AD7667 outputs 16 bits of data, MSB first, on the SDOUT pin. This data is synchronized with the 16 clock pulses provided on the SCLK pin. The output data is valid on both the rising and falling edges of the data clock ...

Page 23

... Figure 40. Master Serial Data Timing for Reading (Read Previous Conversion during Convert) Usually, because the AD7667 is used with a fast throughput, the Master Read During Conversion mode is the most recommen- ded serial mode. In this mode, the serial clock and data toggle at appropriate instants, minimizing potential feedthrough between digital activity and critical conversion decisions ...

Page 24

... Figure 42. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert) While the AD7667 is performing a bit decision important that voltage transients be avoided on digital input/output pins or degradation of the conversion result could occur. This is particularly important during the second half of the conversion ...

Page 25

... Another advantage is the ability to read the data at any speed MHz, which accommodates both the slow digital host interface and the fastest serial reading. Finally, in this mode only, the AD7667 provides a daisy-chain feature using the RDC/SDIN pin for cascading multiple con- verters together. This feature is useful for reducing component count and wiring connections when desired, as, for instance, in isolated multiconverter applications ...

Page 26

... Figure 44 shows an interface diagram between the AD7667 and the SPI equipped ADSP-219x. To accommodate the slower speed of the DSP, the AD7667 acts as a slave device and data must be read after conversion. This mode also allows the daisy- chain feature. The convert command can be initiated in response to an internal timer interrupt ...

Page 27

... ADC to further reduce low frequency ripple. INGND The DVDD supply of the AD7667 can be a separate supply or REF can come from the analog supply AVDD or the digital interface supply OVDD. When the system digital supply is noisy or when ...

Page 28

... SEATING PLANE ORDERING GUIDE Model AD7667AST AD7667ASTRL AD7667ACP AD7667ACPRL 1 EVAL-AD7667CB 2 EVAL-CONTROL BRD2 1 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes. 2 This board allows control and communicate with all Analog Devices evaluation boards ending in the CB designators. ...

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