AD7679 Analog Devices, AD7679 Datasheet
AD7679
Specifications of AD7679
Available stocks
Related parts for AD7679
AD7679 Summary of contents
Page 1
... Instrumentation Spectrum analysis Medical instruments GENERAL DESCRIPTION The AD7679 is an 18-bit, 570 kSPS, charge redistribution SAR, fully differential analog-to-digital converter that operates on a single 5 V power supply. The part contains a high speed 18-bit sampling ADC, an internal conversion clock, an internal reference buffer, error correction circuits, and both serial and parallel system interface ports ...
Page 2
... Rev. A Changes to Zero Error Parameter ........................... 3 MIN MAX Changes to Endnote 3 ...................................................................... 4 Changes to Pin Configuration Section .......................................... 8 Changes to Evaluating the AD7679’s Performance Section ...... 25 Changes to Ordering Guide .......................................................... 26 7/03—Revision 0: Initial Version Typical Connection Diagram ................................................... 17 Power Dissipation versus Throughput .................................... 19 Conversion Control ................................................................... 19 Digital Interface .......................................................................... 20 Parallel Interface ......................................................................... 20 Serial Interface ...
Page 3
... 100 kHz kHz 4.096 V IN REF kHz, –60 dB Input IN Full-Scale Step REF 3 REFBUFIN = 2.5 V 4.05 REFBUFIN 1.8 –1 570 kSPS Throughput Rev Page AD7679 Typ Max Unit Bits +V V REF AVDD+0 μA 1.75 μs 570 kSPS +2.5 LSB 2 +1.75 LSB Bits 0 ...
Page 4
... AD7679 Parameter DIGITAL INPUTS Logic Levels DIGITAL OUTPUTS 5 Data Format Pipeline Delay POWER SUPPLIES Specified Performance AVDD DVDD OVDD Operating Current AVDD 8 DVDD 8 OVDD 8 POWER DISSIPATION 9 TEMPERATURE RANGE Specified Performance 1 See Analog Inputs section. 2 LSB means Least Significant Bit. With the ±4.096 V input range, 1 LSB is 31.25 μV. ...
Page 5
... See Table 1 pF; otherwise, the load maximum. L AD7679 Max Unit ns μ 1.5 μ 1.5 μ 1.5 μ ...
Page 6
... AD7679 Table 4. Serial Clock Timings in Master Read after Convert DIVSCLK[1] DIVSCLK[0] SYNC to SCLK First Edge Delay Minimum Internal SCLK Period Minimum Internal SCLK Period Maximum Internal SCLK HIGH Minimum Internal SCLK LOW Minimum SDOUT Valid Setup Time Minimum SDOUT Valid Hold Time Minimum ...
Page 7
... ABSOLUTE MAXIMUM RATINGS Table 5.AD7679 Absolute Maximum Ratings Parameter Analog Inputs 2 2 IN+ , IN– , REF, REFBUFIN, REFGND to AGND Ground Voltage Differences AGND, DGND, OGND Supply Voltages AVDD, DVDD, OVDD AVDD to DVDD, AVDD to OVDD DVDD to OVDD Digital Inputs 3 Internal Power Dissipation 4 Internal Power Dissipation ...
Page 8
... In other serial modes, these pins are not used AGND 1 PIN 1 AVDD 2 IDENTIFIER MODE0 3 MODE1 4 5 D0/OB/2C AD7679 NC 6 TOP VIEW NC 7 (Not to Scale) D1/A0 8 D2/ ...
Page 9
... Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled also used to gate the external clock. 33 RESET DI Reset Input. When set to a logic HIGH, reset the AD7679. Current conversion, if any, is aborted. If not used, this pin could be tied to DGND. Rev Page AD7679 ...
Page 10
... AD7679 1 Pin No. Mnemonic Type Description Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are inhibited after the current one is completed. 35 CNVST DI Start Conversion. If CNVST is held HIGH when the acquisition phase (t edge on CNVST puts the internal sample/hold into the hold state and initiates a conversion. If CNVST is held LOW when the acquisition phase is complete, the internal sample/hold is put into the hold state and a conversion is started immediately ...
Page 11
... Aperture delay is a measure of the acquisition performance and is measured from the falling edge of the CNVST input to when the input signal is held for a conversion. Transient Response Transient response is the time required for the AD7679 to achieve its rated accuracy after a full-scale step function is applied to its input. Rev Page ...
Page 12
... AD7679 TYPICAL PERFORMANCE CHARACTERISTICS 2.5 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 0 65536 131072 CODE Figure 5. Integral Nonlinearity vs. Code 70000 58510 59001 60000 50000 40000 30000 20000 7584 10000 1FEBD 1FEBE 1FEC0 1FEC1 1FEC2 1FEC3 1FEC4 1FEC5 1FEC6 CODE IN HEX Figure 6. Histogram of 131,072 Conversions of a ...
Page 13
... Figure 14. SNR, S/(N+D), and ENOB vs. Frequency SFDR THIRD HARMONIC THD SECOND HARMONIC 10 100 FREQUENCY (kHz) 03085-0-016 V = 4.096V REF S/(N+D) –50 –40 –30 –20 –10 INPUT LEVEL (dB) Figure 16. SNR and S/(N+D) vs. Input Level AD7679 17.0 16.5 16.0 15.5 15.0 14.5 14.0 1000 140 120 100 1000 SNR 0 03085-0-017 ...
Page 14
... AD7679 100 SNR 99 S/(N+ –55 –35 – TEMPERATURE (°C) Figure 17. SNR, S/(N+D), and ENOB vs. Temperature –100 THD –110 THIRD HARMONIC –120 SECOND HARMONIC –130 –140 –55 –35 – TEMPERATURE (°C) Figure 18. THD and Harmonics vs. Temperature 100000 10000 1000 100 ...
Page 15
... ADC that does not exhibit any pipeline or latency, making it ideal for multiple multiplexed channel applications. The AD7679 can be operated from a single 5 V supply and can be interfaced to either digital logic housed in a 48-lead LQFP tiny 48-lead LFCSP that offers space savings and allows for flexible configurations as either a serial or parallel interface ...
Page 16
... AD7679 Transfer Functions Except in 18-bit interface mode, the AD7679 offers straight binary and twos complement output coding when using OB See Figure 24 and Table 8 for the ideal transfer characteristic. 111...111 111...110 111...101 000...010 000...001 000...000 – ...
Page 17
... MHz typ reduces any undesirable aliasing effect and limits the noise coming from the inputs. Because the input impedance of the AD7679 is very high, the part can be driven directly by a low impedance source without gain error. This allows the user to put an external 1-pole RC ...
Page 18
... MHz of the AD7679 –3dB (26 MHz) or the cutoff frequency of the input filter, if used the noise factor of the amplifiers ( buffer configuration the equivalent input noise voltage of each op amp in N nV/√Hz. ...
Page 19
... Power Supply The AD7679 uses three sets of power supply pins: an analog 5 V supply (AVDD), a digital 5 V core supply (DVDD), and a digital output interface supply (OVDD). The OVDD supply defines the output logic level and allows direct interface with any logic working between 2.7 V and DVDD + 0 reduce the ...
Page 20
... BUS Figure 34. Master Parallel Data Timing for Reading (Continuous Read) PARALLEL INTERFACE The AD7679 is configured to use the parallel interface with an 18-bit, a 16-bit 8-bit bus width, according to Table 7. The data can be read either after each conversion, which is during the next acquisition phase, or during the following conversion, as shown in Figure 35 and Figure 36, respectively ...
Page 21
... RDC/SDIN input, the data can be read after each conversion or during the following conversion. Figure 38 the detailed timing diagrams of these two modes. Usually, because the AD7679 is used with a fast throughput, the mode master read during conversion is the most recommended serial mode. CS, RD ...
Page 22
... Figure 41 show the detailed timing diagrams of these methods. While the AD7679 is performing a bit decision important that voltage transients not occur on digital input/output pins or degradation of the conversion result could occur. This is particularly important during the second half of the conversion phase because the AD7679 provides error correction circuitry that can correct for an improper bit decision made during the first half of the conversion phase ...
Page 23
... D17 D16 t 16 Figure 41. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert) Rev Page INVSCLK = D15 D1 D0 X15 X1 X0 INVSCLK = D15 D1 D0 AD7679 19 20 X17 X16 Y17 Y16 03085-0-042 03085-0-043 ...
Page 24
... Figure 43 shows an interface diagram between the AD7679 and the SPI equipped ADSP-219x. To accommodate the slower speed of the DSP, the AD7679 acts as a slave device, and data must be read after conversion. This mode also allows the daisy- chain feature. The convert command could be initiated in response to an internal timer interrupt ...
Page 25
... This will reduce the effect of feedthrough through the board. The power supply lines to the AD7679 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Good decoupling is also important to lower the supply’ ...
Page 26
... VIEW 1.00 12° MAX 0.85 0.80 SEATING PLANE ORDERING GUIDE Model 1 AD7679ASTZ 1 AD7679ASTZRL 1 AD7679ACPZ 1 AD7679ACPZRL EVAL-AD7679CBZ EVAL-CONTROL BRD2Z EVAL-CONTROL BRD3Z 1 EVAL-CED1Z RoHS Compliant Part. 2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes. ...
Page 27
... NOTES Rev Page AD7679 ...
Page 28
... AD7679 NOTES ©2003–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03085-0-6/09(A) Rev Page ...