AD7466 Analog Devices, AD7466 Datasheet
AD7466
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AD7466 Summary of contents
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... Medical instruments Remote data acquisition Isolated data acquisition GENERAL DESCRIPTION 1 The AD7466/AD7467/AD7468 are 12-/10-/8-bit, high speed, low power, successive approximation analog-to-digital converters (ADCs), respectively. The parts operate from a single 1 3.6 V power supply and feature throughput rates up to 200 kSPS with low power dissipation. The parts contain a low noise, wide bandwidth track-and-hold amplifier, which can handle input frequencies in excess of 3 MHz ...
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... Circuit Information.................................................................... 17 Converter Operation.................................................................. 17 ADC Transfer Function............................................................. 17 Typical Connection Diagram ................................................... 17 Analog Input ............................................................................... 18 Digital Inputs .............................................................................. 18 Normal Mode.............................................................................. 19 Power Consumption .................................................................. 20 Serial Interface ................................................................................ 22 Microprocessor Interfacing....................................................... 23 Application Hints ........................................................................... 25 Grounding and Layout .............................................................. 25 Evaluating the Performance of the AD7466 and AD7467.... 25 Outline Dimensions ....................................................................... 26 Ordering Guide .......................................................................... 27 Rev Page ...
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... DD 0.8 V max 2.7 V ≤ V ±1 μA max Typically 20 nA, V ±1 μA typ 10 pF max Sample tested at 25°C to ensure compliance Rev Page AD7466/AD7467/AD7468 = unless otherwise noted. MIN MAX = 30 kHz sine wave IN ≤ see the Terminology section DD ≤ ≤ ...
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... AD7466/AD7467/AD7468 Parameter LOGIC OUTPUTS Output High Voltage Output Low Voltage Floating-State Leakage Current Floating-State Output Capacitance Output Coding CONVERSION RATE Conversion Time Throughput Rate POWER REQUIREMENTS Normal Mode (Operational) Power-Down Mode Power Dissipation Normal Mode (Operational) Power-Down Mode ...
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... Sample tested at 25°C to ensure compliance Straight (natural) binary 3.52 μs max 12 SCLK cycles with SCLK at 3.4 MHz 275 kSPS max See the Serial Interface section Rev Page AD7466/AD7467/AD7468 = unless otherwise noted. MIN MAX = 1 kHz sine wave DD IN ≤ 3 ≤ ...
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... AD7466/AD7467/AD7468 Parameter POWER REQUIREMENTS Normal Mode (Operational) Power-Down Mode Power Dissipation Normal Mode (Operational) Power-Down Mode B Version Unit Test Conditions/Comments 1.6/3.6 V min/max Digital inputs = 210 μA max 170 μA max 140 μA max ...
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... Sample tested at 25°C to ensure compliance Straight (natural) binary 2.94 μs max 10 SCLK cycles with SCLK at 3.4 MHz 320 kSPS max See the Serial Interface section Rev Page AD7466/AD7467/AD7468 = unless otherwise noted. MIN MAX = 1 kHz sine wave DD IN ≤ 3 ≤ ...
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... AD7466/AD7467/AD7468 Parameter POWER REQUIREMENTS Normal Mode (Operational) Power-Down Mode Power Dissipation Normal Mode (Operational) Power-Down Mode B Version Unit Test Conditions/Comments 1.6/3.6 V min/max Digital inputs = 190 μA max 155 μA max 120 μA max ...
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... OL TO OUTPUT PIN C L 50pF 200μ Figure 2. Load Circuit for Digital Output Timing Specifications Rev Page AD7466/AD7467/AD7468 at which specifications are guaranteed. SCLK at which specifications are guaranteed. at which specifications are guaranteed. = 1.6 V and f = 3.4 MHz, t has to be 192 ns DD SCLK ...
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... SCLK 1 2 ACQUISITION TIME TRACK-AND-HOLD IN TRACK POINT A: THE PART IF FULLY POWERED UP WITH V Timing Example 2 The AD7466 can also operate with slower clock frequencies. As shown in Figure 3, assuming V and a throughput of 50 kSPS gives a cycle time QUIET 7.55 μs, and μs. 8 QUIET μ ...
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... 0 device reliability. −0 −0 0 ±10 mA ESD CAUTION −40°C to +85°C −65°C to +150°C 150°C 229.6°C/W 91.99°C/W 205.9°C/W 43.74°C/W 215°C 220°C 3.5 kV Rev Page AD7466/AD7467/AD7468 ...
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... The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7466 consists of four leading zeros followed by the 12 bits of conversion data, provided MSB first. The data stream from the AD7467 consists of four leading zeros followed by the 10 bits of conversion data, provided MSB first ...
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... Figure 16 shows the maximum current vs. supply voltage for the AD7466 with different SCLK frequencies. Figure 17 shows the shutdown current vs. supply voltage. Figure 18 shows the power consumption vs. throughput rate for the AD7466 with an SCLK of 3.4 MHz and different supply voltages. See the Power Consumption section for more details. 8192 POINT FFT ...
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... V –77 –78 – – 10Ω IN –81 – 510Ω 100Ω –83 –84 10 INPUT FREQUENCY (kHz) Figure 12. AD7466 THD vs. Analog Input Frequency for Various Source Impedances 1 1.8V DD TEMP = 25°C 0 50Hz 100kSPS 0.6 SAMPLE 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 ...
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... TEMP = –40°C SAMPLE 265 240 215 190 165 140 TEMP = +85°C 115 90 65 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 SUPPLY VOLTAGE (V) Figure 15. AD7466 Supply Current vs. Supply Voltage, SCLK 3.4 MHz 560 TEMP = 25°C 500 3.4MHz, = 200kSPS SCLK SAMPLE 440 2.4MHz, = 140kSPS SCLK SAMPLE 380 320 260 200 ...
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... TERMINOLOGY Integral Nonlinearity (INL) The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. For the AD7466/ AD7467/AD7468, the endpoints of the transfer function are zero scale, a point 1 LSB below the first code transition, and full scale, a point 1 LSB above the last code transition. ...
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... DD ANALOG INPUT Figure 21. AD7466/AD7467/AD7468 Transfer Characteristics and, therefore 2.5V REF192 1μF 0.1μF 10μF 0.1μF 240μA TANT SCLK V IN AD7466 SDATA GND CS SERIAL INTERFACE Figure 22. REF192 as Power Supply to AD7466 CHARGE REDISTRIBUTION DAC CONTROL LOGIC should DD 5V SUPPLY μC/μP ...
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... V or 2.5 V (for example, 5 V). The REF19x outputs a steady voltage to the AD7466/AD7467/AD7468. If the low dropout REF192 is used when the AD7466 is converting at a rate of 100 kSPS, the REF192 needs to supply a maximum of 240 μA to the AD7466. The load regulation of the REF192 is typically 10 ppm/mA (REF192 V), which results in an error of 2.4 ppm (6 μ ...
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... The conversion is also initiated at this point. On the third SCLK falling edge after the CS falling edge, the track- and-hold returns to hold mode. For the AD7466, 16 serial clock cycles are required to complete the conversion and access the complete conversion result. The AD7466 automatically enters power-down mode on the 16th SCLK falling edge ...
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... SCLK frequencies, SCLK A and SCLK B, with SCLK A having the higher SCLK frequency. For the same throughput rate, the AD7466 using SCLK A has a shorter conversion time than the AD7466 using SCLK B, and it remains in power-down mode longer. The current consumption in power-down mode is very low ...
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... SCLK frequency is a fixed parameter. Low throughput rates lead to lower current con- sumptions, with a higher percentage of the time in power-down mode. Figure 27 shows two AD7466s running with the same SCLK frequency, but at different throughput rates. The A throughput rate is higher than the B throughput rate. The ...
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... For the AD7466, the final bit in the data transfer is valid on the 16th SCLK falling edge, having been clocked out on the previous (15th) SCLK falling edge ...
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... SPC register) and internal frame signal (TXM = 1 in the SPC register), so both pins are configured as outputs. For the AD7466, the word length should be set to 16 bits ( the SPC register). The standard synchronous serial port interface in this DSP allows only frames with a word length of 16 bits or 8 bits ...
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... FSL1 = 0 and Bit FSL0 = 0 in the CRB register). Set the word length in Control Register A (CRA setting Bits WL2 = 0, WL1 = 1, and WL0 = 0 for the AD7466. The word length for the AD7468 can be set to 12 bits (WL2 = 0, WL1 = 0, and WL0 = 1). This DSP does not offer the option for a 14-bit word length, so the AD7467 word length is set bits like the AD7466 word length ...
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... Analog Devices evaluation boards ending in the CB designator. The software allows the user to perform ac tests (fast Fourier transform) and dc tests (histogram of codes) on the AD7466 and AD7467. See the data sheet in the evaluation board package for more information. Rev Page ...
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... AD7466/AD7467/AD7468 OUTLINE DIMENSIONS INDICATOR 0.15 MAX 2.90 BSC 2.80 BSC 1.60 BSC PIN 1 0.95 BSC 1.90 1.30 BSC 1.15 0.90 1.45 MAX 0.22 0.08 0.50 SEATING 0.30 PLANE COMPLIANT TO JEDEC STANDARDS MO-178-AB Figure 35. 6-Lead Small Outline Transistor Package [SOT-23] (RJ-6) Dimensions shown in millimeters 3.20 3.00 2.80 5. 3.20 4.90 3.00 4.65 2. PIN 1 0.65 BSC 0.95 0.85 1.10 MAX 0.75 8° 0.15 0.38 0.23 0° 0.00 0.22 0.08 SEATING COPLANARITY PLANE 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 36 ...
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... This board is a complete unit that allows control and communicate with all Analog Devices evaluation boards ending in the CB designator. For a complete evaluation kit, order a particular ADC evaluation board (such as EVAL-AD7466CB), the EVAL-CONTROL BRD2, and transformer. See relevant evaluation board data sheets for more information ...
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... AD7466/AD7467/AD7468 NOTES ©2003–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02643-0-5/07(C) Rev Page ...