AD5790 Analog Devices, AD5790 Datasheet - Page 21

• Manufacturer Part Number: AD5790
• Manufacturer: Analog Devices

Specifications of AD5790

• Resolution (bits): 20bit
• Max Pos Supply (v): +16.5V
• Single-supply: No
• Dac Type: Voltage Out
• Dac Input Format: Ser

Data Sheet
Asynchronous DAC Update
In this mode, LDAC is held high while data is being clocked
into the input shift register. The DAC output is asynchronously
updated by taking LDAC low after SYNC has been taken high.
The update now occurs on the falling edge of LDAC .
Reset Function ( RESET )
The
either by asserting the RESET pin or by using the software reset
control function (see
hardwire it to IOV
Asynchronous Clear Function (CLR)
The CLR pin is an active low clear that allows the output to
be cleared to a user defined value. The 20-bit clear code value
is programmed to the clearcode register (see
necessary to maintain
to complete the operation (see
is returned high the output remains at the clear value (if LDAC
is high) until a new value is loaded to the DAC register. The
Table 8. Hardware Control Pins Truth Table
LDAC
X
X
0
0
1
1
0
1
0
1
Table 9. DAC Register
MSB
DB23
R/W
R/W
X is don’t care.
1
1
AD5790
CLR
X
X
0
1
0
1
0
1
0
1
X
1
X
can be reset to its power-on state by two means:
CC
RESET
0
1
1
1
1
1
1
1
1
1
1
1
.
DB22
0
Table 13
CLR low for a minimum amount of time
). If the
Figure 2
Function
The
The
The DAC register is loaded with the clearcode register value and the output is set accordingly.
The output is set according to the DAC register value.
The DAC register is loaded with the clearcode register value and the output is set accordingly.
The output is set according to the DAC register value.
The output remains at the clearcode register value.
The output remains set according to the DAC register value.
The output remains at the clearcode register value.
The DAC register is loaded with the clearcode register value and the output is set accordingly.
The DAC register is loaded with the clearcode register value and the output is set accordingly.
The output remains at the clearcode register value.
The output is set according to the DAC register value.
AD5790
AD5790
RESET pin is not used,
).When the
is in reset mode. The device cannot be programmed.
is returned to its power-on state. All registers are set to their default values.
DB21
0
Table 12
Register address
CLR signal
). It is
Rev. B | Page 21 of 28
DB20
1
output cannot be updated with a new value while the CLR pin is
low. A clear operation can also be performed by setting the CLR
bit in the software control register (see
ON-CHIP REGISTERS
DAC Register
Table 9 outlines how data is written to and read from the DAC
register.
The following equation describes the ideal transfer function of
the DAC:
where:
V
V
D is the 20-bit code programmed to the DAC.
REFN
REFP
V
is the positive voltage applied at the V
is the negative voltage applied at the V
OUT
=
(
V
DB19 to DB0
DAC register data
20 bits of data
REFP
−
2
V
20
REFN
)
×
D
+
V
REFN
Table 13
REFP
REFN
input pin.
).
input pin.
AD5790
LSB