AD5791 Analog Devices, AD5791 Datasheet - Page 20

• Manufacturer Part Number: AD5791
• Manufacturer: Analog Devices

Specifications of AD5791

• Resolution (bits): 20bit
• Dac Update Rate: 1MSPS
• Dac Settling Time: 1µs
• Max Pos Supply (v): +16.5V
• Single-supply: No
• Dac Type: Unbuffered Vout
• Dac Input Format: Ser,SPI

AD5791
THEORY OF OPERATION
The
serial input, voltage output DAC. It operates from a V
voltage of 7.5 V to 16.5 V and a V
Data is written to the
serial interface. The
circuit that ensures the DAC output powers up to 0 V with the
V
DAC ARCHITECTURE
The architecture of the
sections. A simplified circuit diagram is shown in Figure 50.
The six MSBs of the 20-bit data-word are decoded to drive 63
switches, E0 to E62. Each of these switches connects one of 63
matched resistors to either the V
remaining 14 bits of the data-word drive the S0 to S13 switched
of a 14-bit voltage mode R-2R ladder network. To ensure
performance to specification, the reference inputs must be force
sensed with external amplifiers.
Table 7. Input Shift Register Format
MSB
DB23
R/W
Table 8. Decoding the Input Shift Register
R/W
X
0
0
0
0
1
1
1
1
X is don’t care.
1
OUT
AD5791
pin clamped to AGND through a ~6 kΩ internal resistor.
Register Address
0
0
0
0
1
0
0
0
is a high accuracy, fast settling, single, 20-bit,
0
0
1
1
0
0
1
1
AD5791
AD5791
AD5791
DB22
0
1
0
1
0
1
0
1
incorporates a power-on reset
in a 24-bit word format via a 3-wire
consists of two matched DAC
REFP
SS
Description
No operation (NOP; used in readback operations
Write to the DAC register
Write to the control register
Write to the clearcode register
Write to the software control register
Read from the DAC register
Read from the control register
Read from the clearcode register
supply of −16.5 V to −2.5 V.
or V
REFN
voltage. The
DB21
Register address
DD
supply
Rev. C | Page 20 of 28
DB20
V
SERIAL INTERFACE
The
SDIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards, as well as most DSPs (see
timing diagram).
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCLK, which can operate at up to 50 MHz. The
input register consists of a R/ W bit, three address bits, and
twenty register bits as shown in
this operation is shown in
V
V
V
REFNS
REFPF
REFPS
REFNF
AD5791
2R
has a 3-wire serial interface ( SYNC , SCLK, and
2R
S0
14-BIT R-2R LADDER
R
Figure 50. DAC Ladder Structure
2R
S1
DB19
R
.....................
.....................
Figure 2
Table 7
2R
S11
.
R
Register data
SIX MSBs DECODED INTO
63 EQUAL SEGMENTS
. The timing diagram for
2R
E62
Figure 2
DB0
Data Sheet
E61
2R
..........
..........
2R
for a
E0
V
OUT
LSB