AD5624 Analog Devices, AD5624 Datasheet
AD5624
Specifications of AD5624
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AD5624 Summary of contents
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... Relative accuracy: ±12 LSBs maximum. 2. Available in 10-lead MSOP and 10-lead × 3 mm, LFCSP_WD. 3. Low power, typically consumes 1. and 2. Maximum settling time of 4.5 μs (AD5624) and 7 μs (AD5664). One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 AD5624/AD5664 V V ...
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... SYNC Interrupt .......................................................................... 16 Power-On Reset.......................................................................... 16 Software Reset............................................................................. 17 Power-Down Modes .................................................................. 17 LDAC Function .......................................................................... 18 Microprocessor Interfacing....................................................... 19 Applications..................................................................................... 20 Choosing a Reference for the AD5624/AD5664.................... 20 Using a Reference as a Power Supply for the AD5624/AD5664........................................................................ 20 Bipolar Operation Using the AD5624/AD5664..................... 21 Using AD5624/AD5664 with a Galvanically Isolated Interface ....................................................................................... 21 Power Supply Bypassing and Grounding................................ 21 Outline Dimensions ...
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... V 0. ±2 0 Rev Page AD5624/AD5664 unless otherwise noted. MIN MAX Max Unit Conditions/Comments Bits ±12 LSB ±1 LSB Guaranteed monotonic by design Bits ±1 LSB ±0.25 LSB Guaranteed monotonic by design 10 mV ...
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... DD 1 Temperature range: A grade and B grade: −40°C to +105°C. 2 Linearity calculated using a reduced code range: AD5664 (Code 512 to Code 65,024); AD5624 (Code 32 to Code 4064); output unloaded. 3 Guaranteed by design and characterization, not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. ...
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... SCLK falling edge to SYNC rising edge ns min Minimum SYNC high time ns min SYNC rising edge to SCLK fall ignore ns min SCLK falling edge to SYNC fall ignore DB0 Figure 2. Serial Write Operation Rev Page AD5624/AD5664 + V )/2 (see Figure 2 ...
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... AD5624/AD5664 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 5. Parameter V to GND GND OUT V to GND REF Digital Input Voltage to GND Operating Temperature Range Industrial (A Grade, B Grade) Storage Temperature Range Junction Temperature (T max) J Power Dissipation LFCSP_WD Package (4-Layer Board) θ ...
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... Reference Voltage Input. REF OUT REF AD5624 OUT DD AD5664 GND DIN 3 8 TOP VIEW V C SCLK 4 (Not to Scale) 7 OUT V D SYNC 5 6 OUT Figure 3. Pin Configuration th falling edge, the rising edge of SYNC acts as an interrupt Rev Page AD5624/AD5664 ...
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... Rev Page REF T = 25° 500 1000 1500 2000 2500 3000 CODE Figure 7. DNL AD5624 MAX INL REF MAX DNL MIN DNL MIN INL –40 – TEMPERATURE (°C) Figure 8. INL Error and DNL Error vs. Temperature ...
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... Figure 13. Gain Error and Full-Scale Error vs. Supply 1.0 T 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 80 100 2.7 Figure 14. Zero-Scale Error and Offset Error vs. Supply 100 Rev Page AD5624/AD5664 GAIN ERROR FULL-SCALE ERROR 3.2 3.7 4.2 4 25°C A ZERO-SCALE ERROR OFFSET ERROR 3.2 3.7 4.2 4 25° ...
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... AD5624/AD5664 3. 25° 0.39 0.40 0.41 I (mA) DD Figure 16. I Histogram with V DD 0.20 DAC LOADED WITH 5V REF ZERO SCALE – 25°C 0.15 A SINKING CURRENT 0.10 0.05 0 –0.05 –0.10 –0.15 DAC LOADED WITH FULL SCALE – –0.20 SOURCING CURRENT –0.25 – ...
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... A DAC LOADED WITH MIDSCALE 1 Y AXIS = 2µV/DIV 400 450 512 X AXIS = 4s/DIV 800 700 600 500 400 300 200 100 0 8k 10k 10 Rev Page AD5624/AD5664 REF 25° CAPACITANCE (nF) Figure 25 ...
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... AD5624/AD5664 5 0 –5 –10 –15 –20 –25 –30 –35 –40 10k 100k FREQUENCY (Hz) Figure 28. Multiplying Bandwidth 25° 10M Rev Page ...
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... DAC register. Ideally, the output should The zero-code error is always positive in the AD5624/AD5664 because the output of the DAC cannot go below due to a combination of the offset errors in the DAC and the output amplifier. Zero-code error is expressed in mV ...
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... AD5624/AD5664 Digital Crosstalk This is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC measured in standalone mode and is expressed in nV-s. Analog Crosstalk This is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC ...
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... V OUT SERIAL INTERFACE The AD5624/AD5664 have a 3-wire serial interface ( SYNC , SCLK, and DIN) that is compatible with SPI, QSPI, and MICROWIRE interface standards as well as with most DSPs. See Figure 2 for a timing diagram of a typical write sequence. The write sequence begins by bringing the SYNC line low. Data from the DIN line is clocked into the 24-bit shift register on the falling edge of SCLK ...
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... C0 (see Table 7), followed by the 3-bit DAC address (see Table 8), and then the 16-, 12-bit data-word. The data-word comprises the 16-, 12- bit input code followed don’t care bits for the AD5664 and AD5624 respectively (see Figure 31 and Figure 32). These data bits are transferred to the DAC th register on the 24 falling edge of SCLK ...
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... DB20 DB19 Don’t care Command bits (C2 to C0) Table 10. Modes of Operation for the AD5624/AD5664 DB5 When both bits are set to 0, the parts work normally with their normal power consumption of 450 μ However, for the three power-down modes, the supply current falls to 480 (200 ...
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... When the LDAC bit register is set low, the corresponding DAC registers are latched and the input registers can change state without affecting the contents of the Table 13. 24-Bit Input Shift Register Contents for LDAC Setup Command for the AD5624/AD5664 DB23 to DB22 ...
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... The setup for the interface is as follows. TxD of the 80C51/80L51 drives SCLK of the AD5624/AD5664, while RxD drives the serial data line of the part. The SYNC signal is derived from a bit-programmable pin on the port. In this case, port line P3.3 is used. When data is transmitted to the AD5624/AD5664, P3.3 is taken low. The 80C51/80L51 transmits data in 10-bit bytes only ...
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... V. The voltage reference outputs a steady supply voltage for the AD5624/AD5664 (see Table 14 for a suitable reference). If the low dropout 450 μA of current to the AD5624/AD5664, with no load on the output of the DAC. When the DAC output is loaded, the REF195 current required (with a 5 kΩ load on the DAC output) is 450 μ ...
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... The printed circuit board containing the AD5624/ AD5664 should have separate analog and digital sections, each having its own area of the board. If the AD5624/AD5664 system where other devices require an AGND-to-DGND connection, the connection should be made at one point only. ...
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... ORDERING GUIDE Model Temperature Range AD5624BRMZ −40°C to +105°C AD5624BRMZ-REEL7 −40°C to +105°C AD5624BCPZ-250RL7 −40°C to +105°C AD5624BCPZ-REEL7 −40°C to +105°C AD5664ARMZ −40°C to +105°C AD5664ARMZ-REEL7 −40°C to +105°C AD5664BRMZ −40°C to +105°C AD5664BRMZ-REEL7 − ...
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... NOTES Rev Page AD5624/AD5664 ...
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... AD5624/AD5664 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05943-0-6/06(0) Rev Page ...