AD5624R Analog Devices, AD5624R Datasheet - Page 7

• Manufacturer Part Number: AD5624R
• Manufacturer: Analog Devices

Specifications of AD5624R

• Resolution (bits): 12bit
• Dac Update Rate: 287kSPS
• Dac Settling Time: 3µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

TIMING CHARACTERISTICS
All input signals are specified with t
V
Table 5.
Parameter
t
t
t
t
t
t
t
t
t
t
1
2
TIMING DIAGRAM
1
2
3
4
5
6
7
8
9
10
Guaranteed by design and characterization, not production tested.
Maximum SCLK frequency is 50 MHz at V
2
DD
= 2.7 V to 5.5 V; all specifications T
SYNC
SCLK
DIN
Limit at T
V
20
9
9
13
5
5
0
15
13
0
DD
= 2.7 V to 5.5 V
t
8
t
10
DD
R
= 2.7 V to 5.5 V.
t
= t
MIN
DB23
4
MIN
F
, T
= 1 ns/V (10% to 90% of V
MAX
to T
t
5
t
6
MAX
, unless otherwise noted.
t
3
Figure 2. Serial Write Operation
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
t
1
Rev. B | Page 7 of 28
t
2
DD
DB0
t
7
) and timed from a voltage level of (V
t
9
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to SCLK fall ignore
SCLK falling edge to SYNC fall ignore
Conditions/Comments
SCLK cycle time
SCLK high time
Data hold time
1
AD5624R/AD5644R/AD5664R
IL
+ V
IH
)/2 (see Figure 2).